Abstract There is disclosed a video processor capable of arbitrarily expanding or contracting an image in a vertical direction. A horizontal synchronizing signal HS of a video signal CS is inputted to a reference input terminal 63a of a phase comparator 63 of a PLL circuit 62 to take out a clock signal CK having a frequency N1 times larger than that of the horizontal synchronizing signal HS. This clock signal is frequency-divided by N2. Since N2 is set to the number of horizontal synchronizing signals within a vertical synchronous period, the number of sampling lines in a vertical direction becomes equal to N1. Accordingly, when an output signal (line clock signal LCK) of the frequency divider 67 is used as a signal for increment of a vertical address of a video memory 70, enlargement/contraction of an image can be carried out by changing N1.
A video processor having a video memory for storing a luminance signal of a video signal, and performing enlargement or contraction in a vertical direction of an image, said video processor comprising: a synchronous circuit including a first frequency divider for deriving a first clock signal from a horizontal synchronizing signal of the video signal, the first clock signal being synchronous in phase with, and having a higher frequency than, the horizontal synchronizing signal; and an output circuit for frequency dividing the first clock signal to form a second clock signal and for applying the second clock signal to the video memory as a line clock signal for incrementing a vertical address of the video memory.
Claim 2
Dependent Claim
116 words
A video processor having a video memory for storing a luminance signal of a video signal, and performing enlargement or contraction in a vertical direction of an image, said video processor comprising: a synchronous circuit including a first frequency divider for deriving a first clock signal from a horizontal synchronizing signal of the video signal, the first clock signal being synchronous in phase with, and having a higher frequency than, the horizontal synchronizing signal; and an output circuit for frequency dividing the first clock signal to form a second clock signal and for applying the second clock signal to the video memory as a line clock signal for incrementing a vertical address of the video memory.
Claim 3
Dependent Claim
22 words
A video processor according to claim 1 wherein the second clock signal is variable in frequency independently of the horizontal synchronizing signal.
Claim 4
Dependent Claim
35 words
A video processor according to claim 2 wherein said frequency divider in said synchronous circuit has a frequency dividing ratio which is set so the first clock signal is synchronized with the horizontal synchronizing signal.
Claim 5
Dependent Claim
43 words
A video processor according to claim 3 wherein said output circuit frequency divides the first clock signal by a divisor having a value equal to the number of horizontal synchronizing pulses in one period of a vertical synchronizing signal of the video signal.