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US6143609A
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Method for forming semiconductor memory device
Assignee: Panasonic Holdings Corp
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Filing: 1996-12-02
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Granted: 2000-11-07
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Expires: 2016-12-02
Abstract
Abstract A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating film is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.
Inventors
- 👤 Kazuo Sato
- 👤 Kenji Ueda
- 👤 Michio Morita
- 👤 Fumihiko Noro
- 👤 Kyoko Miyamoto
- 👤 Hideaki Onishi
- 👤 Kazuo Umeda
- 👤 Kazuya Kubo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:33
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/68; H10D30/681; H10D30/683; H10B; H10B41/00; H10B41/30; H10B69/00; H10B99/00; H10D30/01; H10D30/021; H10D30/0411; H10D30/6891; H10D30/69
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A method for manufacturing a semiconductor memory, comprising: forming source and drain regions on a semiconductor substrate; forming an active region isolated by an element isolation insulating film on said semiconductor substrate; forming a first insulating film on said active region; sequentially laminating a first conductive film, a second insulating film, a second conductive film and a third insulating film on surfaces of said first insulating film and said element isolation insulating film; etching predetermined portions of said second insulating film, said second conductive film and said third insulating film to form a control gate electrode wherein said etching results in said control gate electrode and said second conductive film having side walls; forming a side wall insulating film on said side walls of said control gate electrode and said second insulating film; etching said first conductive film by using said side wall insulating film as a mask to form a floating gate electrode and to expose only a vertical surface of said floating gate electrode; forming a tunneling insulating film as a tunneling medium only on said vertical surface of said floating gate electrode; and forming an erasing gate electrode made of a third conductive film so as to cover said tunneling insulating film and said side wall insulating film.
Claim 2
Independent Claim
211 words
A method for manufacturing a semiconductor memory, comprising: forming source and drain regions on a semiconductor substrate; forming an active region isolated by an element isolation insulating film on said semiconductor substrate; forming a first insulating film on said active region; sequentially laminating a first conductive film, a second insulating film, a second conductive film and a third insulating film on surfaces of said first insulating film and said element isolation insulating film; etching predetermined portions of said second insulating film, said second conductive film and said third insulating film to form a control gate electrode wherein said etching results in said control gate electrode and said second conductive film having side walls; forming a side wall insulating film on said side walls of said control gate electrode and said second insulating film; etching said first conductive film by using said side wall insulating film as a mask to form a floating gate electrode and to expose only a vertical surface of said floating gate electrode; forming a tunneling insulating film as a tunneling medium only on said vertical surface of said floating gate electrode; and forming an erasing gate electrode made of a third conductive film so as to cover said tunneling insulating film and said side wall insulating film.
Claim 3
Dependent Claim
28 words
The method as defined in claim 1, wherein said tunneling insulating film is formed by oxidizing at least one of the vertical surface of said floating gate electrode.
Claim 4
Dependent Claim
22 words
The method of claim 1, wherein the tunneling medium comprises silicon oxide, silicon nitride, an oxynitride film or a high dielectric film.
Claim 5
Dependent Claim
19 words
The method of claim 1, wherein the second insulating film comprises silicon oxide, silicon nitride or an oxynitride film.
Claim 6
Dependent Claim
25 words
The method of claim 1, wherein the floating gate electrode is formed over a portion of a channel region between the source and drain regions.
Claim 7
Dependent Claim
23 words
The method of claim 1, wherein the floating gate electrode is formed over an entire channel region between the source and drain regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-11-07 | 2004-05-08 | 2004-11-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-11-07 | 2008-05-08 | 2008-11-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-11-07 | 2012-05-08 | 2012-11-07 | $7700.00 | Window Closed / Lapsed |