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US6138232A
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Microprocessor with rate of instruction operation dependent upon interrupt source for power consumption control
Assignee: Texas Instruments Inc
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Filing: 1997-12-19
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Granted: 2000-10-24
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Expires: 2017-12-19
Abstract
Abstract A microprocessor operates at a rate dependent upon the interrupt source of a plurality of interrupt sources. The rate of power consumption by the microprocessor corresponds to the selected rate of instruction operation. A rate table accessed upon receipt of an interrupt stores a table of interrupt source to rate of instruction operation. The rate table may be a read only memory or a read/write memory loaded upon initiation of the microprocessor. The rate of microprocessor instruction operation may be set by frequency of an instruction clock or by a rate of instruction dispatch. For a superscalar microprocessor the rate of instruction operation may be set by setting a number of instructions dispatched per instruction cycle. On receiving an interrupt a rate number is pushed onto a rate stack. On return from the interrupt the rate stack is popped. The microprocessor operates at a rate corresponding to the rate number at a top of the rate stack. The invention may be coordinated with system management mode power control. A predetermined system management mode rate number is pushed onto the rate stack upon receipt of a system management interrupt entering the system management mode. The rate stack is popped upon exit from system management mode to normal mode.
Inventors
- 👤 Jonathan H. Shiell
- 👤 Robert D. Marshall, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 14:36
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/26; G06F1/32; G06F1/3203; G06F1/3234; G06F1/324; G06F9/00; G06F9/06; G06F9/30; G06F9/30145; G06F9/30149; G06F9/38; G06F9/3818; G06F9/382; G06F9/3867; G06F9/3869; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 36
Claim 1
Independent Claim
58 words
A method of operating a microprocessor comprising the steps of: accepting an interrupt from one of a plurality of interrupt sources to change from operating on a current task to operating on a priority task; and setting a rate of microprocessor instruction operation during operation in response to an interrupt dependent upon the interrupt source producing the interrupt.
Claim 2
Independent Claim
58 words
A method of operating a microprocessor comprising the steps of: accepting an interrupt from one of a plurality of interrupt sources to change from operating on a current task to operating on a priority task; and setting a rate of microprocessor instruction operation during operation in response to an interrupt dependent upon the interrupt source producing the interrupt.
Claim 3
Dependent Claim
24 words
The method of operating a microprocessor of claim 1, wherein: the microprocessor rate of power consumption corresponds to the selected rate of instruction operation.
Claim 4
Dependent Claim
75 words
The method of operating a microprocessor of claim 1, wherein: said step of setting a rate of microprocessor instruction operation includes storing a rate table of interrupt source to rate of instruction operation, upon receipt of an interrupt accessing the table to obtain a rate of instruction operation corresponding to the interrupt source producing the interrupt, and operate the microprocessor at a rate corresponding to the rate of instruction operation obtained from the rate table.
Claim 5
Dependent Claim
36 words
The method of operating a microprocessor of claim 3, wherein: said step of storing a rate table of interrupt source to rate of instruction operation includes permanently storing the rate table in a read only memory.
Claim 6
Dependent Claim
34 words
The method of operating a microprocessor of claim 3, wherein: said step of storing a rate table of interrupt source to rate of instruction operation includes temporarily storing the rate table in read/write memory.
Claim 7
Dependent Claim
34 words
The method of operating a microprocessor of claim 5, wherein: said step of storing a rate table of interrupt source to rate of instruction operation includes loading the rate table upon initiation of microprocessor.
Claim 8
Dependent Claim
31 words
The method of operating a microprocessor of claim 1, wherein: said step of setting a rate of microprocessor instruction operation includes setting a frequency of an instruction clock of the microprocessor.
Claim 9
Dependent Claim
42 words
The method of operating a microprocessor of claim 7, wherein: said step of setting a frequency of an instruction clock of the microprocessor includes setting a divide number in a programmable divider in a phase locked loop circuit generating the instruction clock.
Claim 10
Dependent Claim
88 words
The method of operating a microprocessor of claim 7, wherein: said step of setting a frequency of an instruction clock of the microprocessor includes storing a divide number table of interrupt source to divide number, upon receipt of an interrupt accessing the divide number table to obtain a divide number corresponding to the interrupt source producing the interrupt, and setting a divide number in a programmable divider in a phase locked loop circuit generating the instruction clock corresponding to the divide number obtained from the divide number table.
Claim 11
Dependent Claim
120 words
The method of operating a microprocessor of claim 7, wherein: said step of setting a frequency of an instruction clock of the microprocessor includes storing a rate table of interrupt source to rate of instruction operation, upon receipt of an interrupt accessing the table to obtain a rate of instruction operation corresponding to the interrupt source producing the interrupt, storing a divide number table of rate of instruction operation to divide number, accessing the divide number table to obtain a divide number corresponding to the obtained rate of instruction operation, and setting a divide number in a programmable divider in a phase locked loop circuit generating the instruction clock corresponding to the divide number obtained from the divide number table.
Claim 12
Dependent Claim
27 words
The method of operating a microprocessor of claim 1, wherein: said step of setting a rate of microprocessor instruction operation includes setting a rate of instruction dispatch.
Claim 13
Dependent Claim
44 words
The method of operating a microprocessor of claim 1, wherein: the microprocessor is a superscalar microprocessor capable of concurrently executing plural instructions simultaneously; and said step of setting a rate of microprocessor instruction operation includes setting a number of instructions dispatched per instruction cycle.
Claim 14
Dependent Claim
54 words
The method of operating a microprocessor of claim 12, wherein: the microprocessor includes a plurality of independent execution units each independently capable of executing an instruction; and said step number of setting a number of instructions dispatched includes dispatching instructions to a number of said plurality of execution units based upon the selected rate.
Claim 15
Dependent Claim
122 words
The method of operating a microprocessor of claim 13, wherein: said step of dispatching instructions to a number of said plurality of execution units includes dispatching instructions to each of said plurality of execution units for a first highest selected rate, dispatching instructions to a number of execution units less than all of said plurality of execution units for a second selected rate lower than said first selected rate, dispatching an instruction to only one execution unit for a third selected rate lower than said second selected rate, and dispatching an instruction to only one execution unit an instruction cycle followed by dispatching no instruction for at least one instruction cycle for a fourth selected rate lower than said third selected rate.
Claim 16
Dependent Claim
24 words
The method of operating a microprocessor of claim 14, further comprising: supplying electric power only to those execution units to which instructions are dispatched.
Claim 17
Dependent Claim
74 words
The method of operating a microprocessor of claim 13, wherein: said step number of dispatching instructions to a number of said plurality of execution units based upon the selected rate includes dispatching instructions in accordance with speculative execution past a branch instruction for a first highest selected rate, and dispatching no instructions in accordance with speculative execution past a branch instruction for at least on second selected rate lower than the first selected rate.
Claim 18
Dependent Claim
63 words
The method of operating a microprocessor of claim 13, wherein: said step number of dispatching instructions to a number of said plurality of execution units based upon the selected rate includes dispatching instructions out of program order for a first highest selected rate, and dispatching instructions only in program order for at least on second selected rate lower than the first selected rate.
Claim 19
Dependent Claim
65 words
The method of operating a microprocessor of claim 1, wherein: said step of setting a rate of microprocessor instruction operation includes pushing a rate number onto a rate stack upon receiving an interrupt, popping a rate number off the rate stack upon return from an interrupt, and operating the microprocessor at a rate corresponding to the rate number at a top of the rate stack.
Claim 20
Dependent Claim
57 words
The method of operating a microprocessor of claim 18, wherein: a bottom entry of the rate stack stores the greater of the prior bottom entry or a next to bottom entry upon a push of the rate stack and copies the prior bottom entry to the next to bottom entry upon a pop of the rate stack.
Claim 21
Dependent Claim
46 words
The method of operating a microprocessor of claim 18, wherein: a bottom entry of the rate stack returns a rate number corresponding to a maximum rate of instruction operation upon a pop of the rate stack when a bottom entry of the rate stack in empty.
Claim 22
Dependent Claim
50 words
The method of operating a microprocessor of claim 18, further comprising: pushing a predetermined system management mode rate number onto the rate stack upon receipt of a system management interrupt entering a system management mode; and popping the rate stack upon exit from system management mode to a normal mode.
Claim 23
Dependent Claim
21 words
The method of operating a microprocessor of claim 21, wherein: the predetermined system management mode rate is stored in rate register.
Claim 24
Dependent Claim
123 words
A microprocessor comprising: an interrupt interpreter connected to a plurality of interrupt sources and having an output generating an interrupt number corresponding to one of said plurality of interrupt sources generating an interrupt; a rate table memory storing a plurality of rate of instruction operation indicators at locations corresponding to interrupt numbers, said rate table memory having an address input receiving said interrupt number from said interrupt interpreter and an output supplying said rate of instruction operation indicator corresponding to a received interrupt number; and instruction rate control means connected to receive said rate of instruction operation indicator output from said rate table memory for operating the microprocessor at a rate of instruction operation corresponding to a received rate of instruction operation indicator.
Claim 25
Dependent Claim
123 words
A microprocessor comprising: an interrupt interpreter connected to a plurality of interrupt sources and having an output generating an interrupt number corresponding to one of said plurality of interrupt sources generating an interrupt; a rate table memory storing a plurality of rate of instruction operation indicators at locations corresponding to interrupt numbers, said rate table memory having an address input receiving said interrupt number from said interrupt interpreter and an output supplying said rate of instruction operation indicator corresponding to a received interrupt number; and instruction rate control means connected to receive said rate of instruction operation indicator output from said rate table memory for operating the microprocessor at a rate of instruction operation corresponding to a received rate of instruction operation indicator.
Claim 26
Dependent Claim
16 words
The microprocessor of claim 23, wherein: said rate table memory consists of a read only memory.
Claim 27
Dependent Claim
15 words
The microprocessor of claim 23, wherein: said rate table memory consists of a read/write memory.
Claim 28
Dependent Claim
17 words
The microprocessor of claim 25, further comprising: means for loading said rate table upon initiation of microprocessor.
Claim 29
Dependent Claim
80 words
The microprocessor of claim 23, further comprising: an external clock input for receiving an external clock signal; a phase locked loop circuit having an input connected to said external clock input, a programmable divider connected to said rate table memory and an output generating an internal clock signal in phase synchronization with said external clock signal, said programmable divider setting a relationship between an external clock frequency and an internal clock frequency dependent upon said rate of instruction operation indicator.
Claim 30
Dependent Claim
134 words
The microprocessor of claim 23, further comprising: an external clock input for receiving an external clock signal; a divide number memory storing a plurality of divide numbers at locations corresponding to said rate of instruction operation indicators, said divide number memory having an address input receiving said rate of instruction operation indicator from said rate table memory and an output supplying said divide number corresponding to a received rate of instruction operation indicator; and a phase locked loop circuit having an input connected to said external clock input, a programmable divider connected to said divide number memory and an output generating an internal clock signal in phase synchronization with said external clock signal, said programmable divider setting a relationship between an external clock frequency and an internal clock frequency dependent upon said divide number.
Claim 31
Dependent Claim
58 words
The microprocessor of claim 23, further comprising: a plurality of execution units, each execution unit independently capable of executing an instruction; wherein said instruction rate control means includes a scheduler connected to said plurality of execution units, said scheduler dispatching instructions to said plurality of execution units at a rate corresponding to said rate of instruction operation indicator.
Claim 32
Dependent Claim
108 words
The microprocessor of claim 29, wherein: said scheduler dispatches instructions to each of said plurality of execution units for a first highest selected rate, dispatches instructions to a number of execution units less than all of said plurality of execution units for a second selected rate lower than said first selected rate, dispatches an instruction to only one of said plurality of execution units for a third selected rate lower than said second selected rate, and dispatches an instruction to only one of said plurality of execution units in only one of a plurality of instruction cycles for a fourth selected rate lower than said third selected rate.
Claim 33
Dependent Claim
144 words
The microprocessor of claim 23, further comprising: an interrupt return instruction detector receiving instructions executed by the microprocessor, said interrupt return instruction detector generating an output signal upon each detection of an instruction returning from an interrupt; and a rate number push/pop stack memory having a push input connected to said interrupt interpreter, a pop input connected to said interrupt return detector, a data input connected to said rate table memory, a data output connected to said instruction rate control means and a plurality of first-in-last-out data entries, said rate number push/pop stack memory pushing said rate of instruction operation indicator onto a first stack entry whenever said interrupt interpreter signals the receiving of an interrupt, popping said first stack entry whenever said interrupt return instruction decoder signals returning from an interrupt, and supplying said first stack entry to said instruction rate control means.
Claim 34
Dependent Claim
64 words
The microprocessor of claim 31, wherein: said rate stack wherein a bottom entry stores a rate of instruction operation indicator having the greater rate of instruction operation of the prior bottom entry or a next to bottom entry upon a push of said rate stack and copies said prior bottom entry to the next to bottom entry upon a pop of said rate stack.
Claim 35
Dependent Claim
41 words
The microprocessor of claim 31, wherein: said rate stack wherein a bottom entry returns a rate of instruction operation indicator corresponding to a maximum rate of instruction operation upon a pop of said rate stack when said bottom entry is empty.
Claim 36
Dependent Claim
194 words
The microprocessor of claim 31, further comprising: a system management interrupt input receiving a system management interrupt; a system management mode rate memory storing a rate number; a multiplexer having a first input receiving said interrupt number of said interrupt interpreter, a second input receiving said rate number of said system management mode rate memory, a control input connected to said system management interrupt input and an output outputting said interrupt number at said first input if said system management interrupt it not active and outputting said rate number at said second input if said system management interrupt is active; a first AND gate having a first input connected to said interrupt interpreter, a second input connected to said system management interrupt input and an output connected to said push input of said rate number push/pop stack memory; an invertor having an input connected to said system management interrupt input and an output; and a second AND gate having a first input connected to said interrupt return instruction detector, a second input connected to said output of said invertor and an output connected to said pop input of said rate number push/pop stack memory.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |