US6137355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dual-mode amplifier with high efficiency and high linearity
Assignee: Individual
•
Filing: 1999-10-28
•
Granted: 2000-10-24
•
Expires: 2019-10-28
Abstract
Abstract An amplifier circuit having a high linearity mode of operation and a high efficiency mode of operation. The amplifier circuit comprises an amplifier having a variable active device periphery and a variable supply voltage; and a control circuit, coupled to the amplifier, for decreasing the variable active device periphery and increasing the variable supply voltage when in the high linearity mode of operation, and for increasing the variable active device periphery and decreasing the variable supply voltage when in the high efficiency mode of operation.
Inventors
- 👤 John F. Sevic
- 👤 Richard J. Camarillo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:33
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/211; H03F1/00; H03F1/02; H03F1/0205; H03F1/0211; H03F1/0216; H03F1/0277; H03F3/72
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
153 words
An amplifier circuit comprising: a first amplifier stage having a first supply voltage input for receiving a supply voltage and a first signal input for receiving a signal to be amplified and a bias signal; a second amplifier stage having a second supply voltage input for receiving said supply voltage and a second signal input for receiving said signal to be amplified and said bias signal; and a control circuit having a supply voltage output coupled to said first and second supply voltage inputs and having first and second bias signal outputs respectively coupled to said first and second signal inputs, and having a mode select input for receiving a mode select signal, said control circuit for varying said supply voltage and said bias signal in response to said mode select signal wherein said control circuit biases on both said first and second amplifiers in response to a high efficiency mode select signal.
Claim 2
Dependent Claim
153 words
An amplifier circuit comprising: a first amplifier stage having a first supply voltage input for receiving a supply voltage and a first signal input for receiving a signal to be amplified and a bias signal; a second amplifier stage having a second supply voltage input for receiving said supply voltage and a second signal input for receiving said signal to be amplified and said bias signal; and a control circuit having a supply voltage output coupled to said first and second supply voltage inputs and having first and second bias signal outputs respectively coupled to said first and second signal inputs, and having a mode select input for receiving a mode select signal, said control circuit for varying said supply voltage and said bias signal in response to said mode select signal wherein said control circuit biases on both said first and second amplifiers in response to a high efficiency mode select signal.
Claim 3
Dependent Claim
85 words
An amplifier circuit having a high linearity mode of operation and a high efficiency mode of operation, said amplifier circuit comprising: an amplifier having a variable active device periphery and a variable supply voltage; and a control circuit, coupled to said amplifier, for decreasing said variable active device periphery and increasing said variable supply voltage when in said high linearity mode of operation, and for increasing said variable active device periphery and decreasing said variable supply voltage when in said high efficiency mode of operation.
Claim 4
Dependent Claim
85 words
An amplifier circuit having a high linearity mode of operation and a high efficiency mode of operation, said amplifier circuit comprising: an amplifier having a variable active device periphery and a variable supply voltage; and a control circuit, coupled to said amplifier, for decreasing said variable active device periphery and increasing said variable supply voltage when in said high linearity mode of operation, and for increasing said variable active device periphery and decreasing said variable supply voltage when in said high efficiency mode of operation.
Claim 5
Dependent Claim
65 words
The amplifier circuit of claim 2 wherein said variable active device periphery comprises a plurality of transistor stages, and wherein said control circuit decreases said variable active device periphery by biasing off at least one of said plurality of transistor stages, and wherein said control circuit increases said variable active device periphery by biasing on said at least one of said plurality of transistor stages.
Claim 6
Dependent Claim
32 words
The amplifier circuit of claim 3 wherein said control circuit is responsive to a mode select signal indicative of said high efficiency mode of operation or said high linearity mode of operation.
Claim 7
Independent Claim
65 words
A method for operating an amplifier circuit having a variable active device periphery and a variable supply voltage, said method comprising the steps of: decreasing said variable active device periphery and increasing said variable supply voltage when in a high linearity mode of operation; and increasing said variable active device periphery and decreasing said variable supply voltage when in a high efficiency mode of operation.
Claim 8
Independent Claim
65 words
A method for operating an amplifier circuit having a variable active device periphery and a variable supply voltage, said method comprising the steps of: decreasing said variable active device periphery and increasing said variable supply voltage when in a high linearity mode of operation; and increasing said variable active device periphery and decreasing said variable supply voltage when in a high efficiency mode of operation.
Claim 9
Dependent Claim
64 words
The method of claim 5 wherein said variable active device periphery comprises a plurality of transistor stages, and wherein the step of decreasing said variable active device periphery comprises biasing off at least one of said plurality of transistor stages, and wherein said step of increasing said variable active device periphery comprises biasing on said at least one of said plurality of transistor stages.
Claim 10
Dependent Claim
20 words
The method of claim 5 further comprising the step of decreasing a quiescent current of said variable active device periphery.
References Cited (Backward Citations)
US4439744A
Cited
US5256987A
Cited
US5251331A
Cited
US5438684A
Cited
US5548246A
Cited
US5774017A
Cited
US6069525A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |