US5548246A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power amplifier including an impedance matching circuit and a switch FET
Assignee: Mitsubishi Electric Corp
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Filing: 1995-05-10
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Granted: 1996-08-20
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Expires: 2015-05-10
Abstract
Abstract A power amplifier comprises opposite input and output terminals, a first amplifier circuit connected between the input terminal and the output terminal and comprising a first amplifier FET and a first matching circuit, and a second amplifier circuit connected between the input terminal and the output terminal and comprising a second amplifier FET, a second matching circuit, and a switching circuit. In this power amplifier, the first amplifier circuit outputs an output signal of a first power level when the first amplifier FET is operated while the second amplifier FET is not operated and the switching circuit is turned off, and the second amplifier circuit outputs an output signal of a second power level when the first amplifier FET is not operated while the second amplifier FET is operated and the switching circuit is turned on. Therefore, impedances of the output side matching circuits of the first and second amplifier circuits which output amplified signals of different power levels can be optimized with high precision. As the result, in both the high-power output operation and the low-power output operation, the efficiencies of the first and second amplifier circuits are significantly improved.
Inventors
- 👤 Kazuya Yamamoto
- 👤 Noriyuki Tanino
- 👤 Tetsuya Umemoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:12
CPC Classifications
H; H03; H03F; H03F3/00; H03F3/20; H03F3/21; H03F3/211; H03F1/00; H03F1/02; H03F1/0205; H03F1/0277; H03F1/56
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
337 words
A power amplifier comprising: an input terminal for receiving an input signal to be amplified; an output terminal for supplying an amplified signal; a first amplifier circuit connected between the input terminal and the output terminal and comprising 1) a first amplifier FET having an input end, an output end, and a first gate width, and 2) a first matching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the first amplifier FET, the output end of the first amplifier FET is connected to the input end of the first matching circuit, and the output end of the first matching circuit is connected to the output terminal; and a second amplifier circuit connected between the input terminal and the output terminal and comprising 1) a second amplifier FET having an input end, an output end, and a second gate width, 2) a second matching circuit having an input end and an output end, and 3) a first switching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the second amplifier FET, the output end of the second amplifier FET is connected to the input end of the second matching circuit, the output end of the second matching circuit is connected to the input end of the first switching circuit, and the output end of the first switching circuit is connected to the output terminal and wherein the first gate width is greater than the second gate width whereby said first amplifier circuit outputs an output signal of a first power level with high efficiency when the first amplifier FET is operated, the second amplifier FET is not operated, and the first switching circuit is electrically open and the second amplifier circuit outputs an output signal of a second power level with high efficiency when the first amplifier FET is not operated, the second amplifier FET is operated, and the first switching circuit is electrically closed.
Claim 2
Dependent Claim
337 words
A power amplifier comprising: an input terminal for receiving an input signal to be amplified; an output terminal for supplying an amplified signal; a first amplifier circuit connected between the input terminal and the output terminal and comprising 1) a first amplifier FET having an input end, an output end, and a first gate width, and 2) a first matching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the first amplifier FET, the output end of the first amplifier FET is connected to the input end of the first matching circuit, and the output end of the first matching circuit is connected to the output terminal; and a second amplifier circuit connected between the input terminal and the output terminal and comprising 1) a second amplifier FET having an input end, an output end, and a second gate width, 2) a second matching circuit having an input end and an output end, and 3) a first switching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the second amplifier FET, the output end of the second amplifier FET is connected to the input end of the second matching circuit, the output end of the second matching circuit is connected to the input end of the first switching circuit, and the output end of the first switching circuit is connected to the output terminal and wherein the first gate width is greater than the second gate width whereby said first amplifier circuit outputs an output signal of a first power level with high efficiency when the first amplifier FET is operated, the second amplifier FET is not operated, and the first switching circuit is electrically open and the second amplifier circuit outputs an output signal of a second power level with high efficiency when the first amplifier FET is not operated, the second amplifier FET is operated, and the first switching circuit is electrically closed.
Claim 3
Dependent Claim
154 words
The power amplifier of claim 1 wherein the first power level is larger than the second power level, said power amplifier further comprising: a third matching circuit having an input end connected to the input terminal and an output end connected to the input end of the first amplifier FET; and a second switching circuit having an input end and an output end and a fourth matching circuit having an input end and an output end, the input end of the second switching circuit being connected to the input terminal, the output end of the second switching circuit being connected to the input end of the fourth matching circuit, and the output end of the fourth matching circuit being connected to the input end of the second amplifier FET, wherein the second switching circuit is turned off when the first amplifier FET is operated and turned on when the second amplifier FET is operated.
Claim 4
Dependent Claim
339 words
A power amplifier comprising: an input terminal for receiving a signal to be amplified; an output terminal for supplying an amplified signal; a first amplifier circuit connected between the input terminal and the output terminal and comprising 1) a first amplifier FET having an input end add an output end, the first amplifier FET including an FET switch for branching a gate bias applied to the first amplifier FET and 2) a first matching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the first amplifier FET, the output end of the first amplifier FET is connected to the input end of the first matching circuit, and the output end of the first matching circuit is connected to the output terminal; and a second amplifier circuit connected between the input terminal and the output terminal and comprising 1) a second amplifier FET having an input end and an output end, a second matching circuit having an input end and an output end, and a first switching circuit having an input end and an input end, wherein the input terminal connected to the input end of the second amplifier FET, the output end of the second amplifier FET is connected to the input end of the second matching circuit, the output end of the second matching circuit is connected to the input end of the first switching circuit, and the output end of the first switching circuit is connected to the output terminal, whereby the first amplifier circuit outputs an output signal of a first power level with high efficiency when the first amplifier FET is operated, while the second amplifier FET is not operated, and the first switching circuit is electrically open, and said second amplifier circuit outputs an output signal of a second power level, lower than the first power level, with high efficiency when the first amplifier FET is not operated, while the second amplifier FET is operated and the first switching circuit is electrically closed.
Claim 5
Dependent Claim
339 words
A power amplifier comprising: an input terminal for receiving a signal to be amplified; an output terminal for supplying an amplified signal; a first amplifier circuit connected between the input terminal and the output terminal and comprising 1) a first amplifier FET having an input end add an output end, the first amplifier FET including an FET switch for branching a gate bias applied to the first amplifier FET and 2) a first matching circuit having an input end and an output end, wherein the input terminal is connected to the input end of the first amplifier FET, the output end of the first amplifier FET is connected to the input end of the first matching circuit, and the output end of the first matching circuit is connected to the output terminal; and a second amplifier circuit connected between the input terminal and the output terminal and comprising 1) a second amplifier FET having an input end and an output end, a second matching circuit having an input end and an output end, and a first switching circuit having an input end and an input end, wherein the input terminal connected to the input end of the second amplifier FET, the output end of the second amplifier FET is connected to the input end of the second matching circuit, the output end of the second matching circuit is connected to the input end of the first switching circuit, and the output end of the first switching circuit is connected to the output terminal, whereby the first amplifier circuit outputs an output signal of a first power level with high efficiency when the first amplifier FET is operated, while the second amplifier FET is not operated, and the first switching circuit is electrically open, and said second amplifier circuit outputs an output signal of a second power level, lower than the first power level, with high efficiency when the first amplifier FET is not operated, while the second amplifier FET is operated and the first switching circuit is electrically closed.
Claim 6
Dependent Claim
49 words
The power amplifier of claim 1 further comprising: a fourth switching circuit connected between the input terminal and the input end of the first amplifier FET, the fourth switching circuit being active when the first amplifier FET is operated and being inactive when the second amplifier FET is operated.
Claim 7
Dependent Claim
162 words
A power amplifier comprising: an input terminal for receiving an input signal to be amplified; an output terminal for supplying an amplified signal; an amplifier FET for receiving the input signal from the input terminal, amplifying the input signal, and outputting an amplified signal having a power level; a plurality of matching circuits, each matching circuit having a different impedance, each matching circuit having an input end and an output end; a first switching circuit connected to the input ends of the plurality of matching circuits for selecting one of the plurality of matching circuits in response to the power level of the amplified signal and connecting the amplifier FET to the input end of the selected matching circuit, the selected matching circuit providing for high-efficiency operation of the amplifier FET; and a second switching circuit connected to the output ends of the plurality of matching circuits for selectively connecting the output end of the selected matching circuit to the output terminal.
Claim 8
Dependent Claim
162 words
A power amplifier comprising: an input terminal for receiving an input signal to be amplified; an output terminal for supplying an amplified signal; an amplifier FET for receiving the input signal from the input terminal, amplifying the input signal, and outputting an amplified signal having a power level; a plurality of matching circuits, each matching circuit having a different impedance, each matching circuit having an input end and an output end; a first switching circuit connected to the input ends of the plurality of matching circuits for selecting one of the plurality of matching circuits in response to the power level of the amplified signal and connecting the amplifier FET to the input end of the selected matching circuit, the selected matching circuit providing for high-efficiency operation of the amplifier FET; and a second switching circuit connected to the output ends of the plurality of matching circuits for selectively connecting the output end of the selected matching circuit to the output terminal.
Claim 9
Dependent Claim
17 words
The poor amplifier of claim 1 wherein the first amplifier FET includes a plurality of FET cells.
Claim 10
Dependent Claim
17 words
The power amplifier of claim 1 wherein the second amplifier FET includes a plurality of FET cells.
References Cited (Backward Citations)
JPS60193369A
Cited
US4598252A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-20 | 2000-02-19 | 2000-08-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-20 | 2004-02-19 | 2004-08-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-20 | 2008-02-19 | 2008-08-20 | $7700.00 | Window Closed / Lapsed |