Variable gain power amplifier

Claim 2

A variable gain power amplifier comprising: a plurality of amplifiers of known gain each amplifier having an input and an output; a common input; a common output, said common input being connected to said amplifier inputs, said amplifier outputs being connected to said common output by a plurality of switches, each switch connected from one of said plurality of amplifiers to said common output, said switches being closed to increase the output signal power on said common output by an amount equal to the increase in power delivered by the corresponding amplifier; and gain selection means connected to said amplifiers for selectively reducing the power outputs thereof to zero while opening the ones of said switches connected to amplifiers having their gain reduced to zero.

Claim 3

A variable gain power amplifier comprising: first and second common inputs; a common output amplifiers A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18 and A19, each having an input, an output and a variable gain control input, said amplifiers A1, A3 and A5 having their inputs connected to said first common input, said amplifiers A2 and A4 having their inputs respectively connected to the outputs of amplifiers A1 and A3; switches S1A, S1B and S1C connected respectively between the outputs of amplifiers A2, A4 and A5 and the input of said amplifier A19: a switch S2 having a pole connected to the output of said amplifier A19, and first and second contacts; first means for rendering the outputs of said amplifiers A1 and A2 zero while rendering said switch S1A open, and vice versa; second means for rendering the output of said amplifiers A3 and A4 zero while rendering said switch S1B open, and vice versa; third means for rendering the output of amplifier A5 zero while rendering said switch S1C open, and vice versa; a gain selection circuit for selectively causing only one of said first, second and third means to be operative to close one of said circuits S1A, S1B and S1C at a time; a fine gain circuit means connected to the variable gain control input of amplifier A19 for fine gain control of amplifier A19, said first contact of switch S2 being connected to said common output via a switch A, and said second contact of switch S2 being connected to said second common input, said second common input being connected to the inputs of said amplifiers A6, A8, A10, A13 and A16, said amplifiers A6 and A7 being connected in cascade to said common output via a switch B, said amplifiers A8 and A9 being connected in cascade to said common output via a switch C, said amplifiers A10, A11 and A12 being connected in cascade to said common output via a switch D, said amplifiers A13, A14 and A15 being connected in cascade to said common output via a switch E, and said amplifiers A16, A17 and A18 being connected to said common output via a switch F; and means connected to all the variable gain control inputs of said amplifiers A6-A7, A8-A9, A10-A11-A12, A13-A14-A15, A16-A17-A18 and said switches A, B, C, D, E and F for rendering selected ones of said amplifier outputs zero when a corresponding one of said switches A-F is open.

Claim 4

A variable gain power amplifier comprising: first and second common inputs; a common output amplifiers A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, A12, A13, A14, A15, A16, A17, A18 and A19, each having an input, an output and a variable gain control input, said amplifiers A1, A3 and A5 having their inputs connected to said first common input, said amplifiers A2 and A4 having their inputs respectively connected to the outputs of amplifiers A1 and A3; switches S1A, S1B and S1C connected respectively between the outputs of amplifiers A2, A4 and A5 and the input of said amplifier A19: a switch S2 having a pole connected to the output of said amplifier A19, and first and second contacts; first means for rendering the outputs of said amplifiers A1 and A2 zero while rendering said switch S1A open, and vice versa; second means for rendering the output of said amplifiers A3 and A4 zero while rendering said switch S1B open, and vice versa; third means for rendering the output of amplifier A5 zero while rendering said switch S1C open, and vice versa; a gain selection circuit for selectively causing only one of said first, second and third means to be operative to close one of said circuits S1A, S1B and S1C at a time; a fine gain circuit means connected to the variable gain control input of amplifier A19 for fine gain control of amplifier A19, said first contact of switch S2 being connected to said common output via a switch A, and said second contact of switch S2 being connected to said second common input, said second common input being connected to the inputs of said amplifiers A6, A8, A10, A13 and A16, said amplifiers A6 and A7 being connected in cascade to said common output via a switch B, said amplifiers A8 and A9 being connected in cascade to said common output via a switch C, said amplifiers A10, A11 and A12 being connected in cascade to said common output via a switch D, said amplifiers A13, A14 and A15 being connected in cascade to said common output via a switch E, and said amplifiers A16, A17 and A18 being connected to said common output via a switch F; and means connected to all the variable gain control inputs of said amplifiers A6-A7, A8-A9, A10-A11-A12, A13-A14-A15, A16-A17-A18 and said switches A, B, C, D, E and F for rendering selected ones of said amplifier outputs zero when a corresponding one of said switches A-F is open.

Claim 5

A variable gain power amplifier comprising: a main input; a main output; a first set of n FET switches connected to said main input; a programmer having a coded gain input to regulate the power gain from said main input to said main output, said programmer having a first set of n outputs to control which of said first set of FET switches is turned on; n input matching networks, said first set of FET switches having outputs connected to respective ones of said n input matching networks; a silicon chip carrying n FET amplifiers connected to respective ones of said matching networks; n output FET switches connected to said main output; and n output matching networks each connected between a corresponding one of said FET amplifiers and a corresponding one of said output FET switches, said programmer having a second set of n outputs to turn on selected ones of said FET amplifiers and a third set of n outputs to turn on selected ones of said output FET switches corresponding to turned on ones of said FET amplifiers.

Claim 6

A variable gain power amplifier comprising: a main input; a main output; a first set of n FET switches connected to said main input; a programmer having a coded gain input to regulate the power gain from said main input to said main output, said programmer having a first set of n outputs to control which of said first set of FET switches is turned on; n input matching networks, said first set of FET switches having outputs connected to respective ones of said n input matching networks; a silicon chip carrying n FET amplifiers connected to respective ones of said matching networks; n output FET switches connected to said main output; and n output matching networks each connected between a corresponding one of said FET amplifiers and a corresponding one of said output FET switches, said programmer having a second set of n outputs to turn on selected ones of said FET amplifiers and a third set of n outputs to turn on selected ones of said output FET switches corresponding to turned on ones of said FET amplifiers.