US6137322A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic output control circuit
Assignee: Texas Instruments Inc
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Filing: 1999-05-28
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Granted: 2000-10-24
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Expires: 2019-05-28
Abstract
Abstract The output control circuit includes: a first high side transistor 56 coupled to an output node 68; a second high side transistor 59 coupled in parallel with the first high side transistor 56; a first transmission gate 72 coupled between a control node of the first high side transistor 56 and a control node of the second high side transistor 59, the first transmission gate 72 is controlled by feedback from the output node 68; a first low side transistor 50 coupled to the output node 68; a second low side transistor 53 coupled in parallel with the first low side transistor 50; a second transmission gate 74 coupled between a control node of the first low side transistor 50 and a control node of the second low side transistor 53, the second transmission gate 74 is controlled by feedback from the output node 68.
Inventors
- 👤 Timothy A. Ten Eyck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 20:09
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/16; H03K17/161; H03K17/165; H03K17/166; H03K17/167
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
155 words
An output control circuit comprising: a first high side transistor coupled to an output node; a second high side transistor coupled in parallel with the first high side transistor; a first transmission gate coupled between a control node of the first high side transistor and a control node of the second high side transistor, the first transmission gate is controlled by feedback from the output node; a first low side transistor coupled to the output node; a second low side transistor coupled in parallel with the first low side transistor; a second transmission gate coupled between a control node of the first low side transistor and a control node of the second low side transistor, the second transmission gate is controlled by feedback from the output node; and a transistor coupled between the control node of the second high side transistor and a supply node, the transistor is controlled by feedback from the output node.
Claim 2
Dependent Claim
155 words
An output control circuit comprising: a first high side transistor coupled to an output node; a second high side transistor coupled in parallel with the first high side transistor; a first transmission gate coupled between a control node of the first high side transistor and a control node of the second high side transistor, the first transmission gate is controlled by feedback from the output node; a first low side transistor coupled to the output node; a second low side transistor coupled in parallel with the first low side transistor; a second transmission gate coupled between a control node of the first low side transistor and a control node of the second low side transistor, the second transmission gate is controlled by feedback from the output node; and a transistor coupled between the control node of the second high side transistor and a supply node, the transistor is controlled by feedback from the output node.
Claim 3
Dependent Claim
34 words
The device of claim 1 further comprising a transistor coupled between the control node of the second low side transistor and a ground node, the transistor is controlled by feedback from the output node.
Claim 4
Dependent Claim
21 words
The device of claim 1 wherein the first transmission gate includes an NMOS transistor coupled in parallel with a PMOS transistor.
Claim 5
Dependent Claim
25 words
The device of claim 3 further comprising a first inverter coupled between a gate of the NMOS transistor and a gate of the PMOS transistor.
Claim 6
Dependent Claim
22 words
The device of claim 4 further comprising a second inverter coupled between the output node and the gate of the NMOS transistor.
Claim 7
Dependent Claim
21 words
The device of claim 1 wherein the second transmission gate includes an NMOS transistor coupled in parallel with a PMOS transistor.
Claim 8
Dependent Claim
25 words
The device of claim 6 further comprising a first inverter coupled between a gate of the PMOS transistor and a gate of the NMOS transistor.
Claim 9
Dependent Claim
22 words
The device of claim 7 further comprising a second inverter coupled between the output node and the gate of the PMOS transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-10-24 | 2004-04-24 | 2004-10-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-10-24 | 2008-04-24 | 2008-10-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-10-24 | 2012-04-24 | 2012-10-24 | $7700.00 | Window Closed / Lapsed |