Programmable divider circuit with a tri-state inverter

Claim 2

A programmable dividing circuit comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 3

The dividing circuit according to claim 1 wherein a total of M stages are connected in sequence with the tri-state inverter stage, the output of a last stage in the sequence of the total of M stages connected to one input of the switching circuit, the other input of the switching circuit connected to an output of an (M-p)th stage in the sequence of the total of M stages, where p is an odd integer and M-p=N.

Claim 4

The dividing circuit according to claim 2 wherein p=1.

Claim 5

The dividing circuit according to claim 2 wherein the tri-state inverter stage is a last stage in the divide-by-M sequence, the tri-state inverter stage generating an output signal having a duty cycle of 50%.

Claim 6

The dividing circuit according to claim 1 wherein a common sequence of an even number x of transistor stages has an output node connected to first and second circuit branches, the first branch comprising q transistor stages, wherein q is an odd integer greater than or equal to 1, and the second branch comprising r transistor stages and said tri-state inverter, wherein r is an even integer greater than or equal to zero, an output of the first and second branches connected to respective inputs of the switching circuit, wherein N=x+q and M=x+r.

Claim 7

The dividing circuit according to claim 5 wherein q=1 and r=0, whereby N=M+1.

Claim 8

The dividing circuit according to claim 1 wherein the switching circuit is a multiplexer.

Claim 9

The dividing circuit according to claim 1 wherein the switching circuit has a select input to receive a programming signal to effect the selective connection.

Claim 10

The dividing circuit according to claim 1 wherein the switching circuit has at least one further input to receive an output of one of the stages in the divide-by-N or divide-by-M sequence to allow selection of a further dividing factor.

Claim 11

The dividing circuit according to claim 1, further comprising another switching circuit having inputs connected to different stages in the divide-by-N or divide-by-M sequence and an output connected to a subsequent stage to allow selection of a further dividing factor.

Claim 12

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input to receive a feedback signal, the phase detector operable to generate an error signal according to a relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and a dividing circuit connected to receive an output from the voltage controlled oscillator and to divide the output by a predetermined integer to generate the feedback signal, the dividing circuit comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 13

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input to receive a feedback signal, the phase detector operable to generate an error signal according to a relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and a dividing circuit connected to receive an output from the voltage controlled oscillator and to divide the output by a predetermined integer to generate the feedback signal, the dividing circuit comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 14

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input for receiving a feedback signal, the phase detector being operable to generate an error signal according to the relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and an input divider to divide the reference signal prior to the phase detector, the input divider comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 15

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input for receiving a feedback signal, the phase detector being operable to generate an error signal according to the relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and an input divider to divide the reference signal prior to the phase detector, the input divider comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence, whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 16

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input to receive a feedback signal, the phase detector operable to generate an error signal according to the relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and an output divider connected to receive the output from the voltage controlled oscillator to generate a divided output signal, the output divider comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 17

A phase-locked-loop circuit, comprising: a phase detector having a first input to receive a reference signal and a second input to receive a feedback signal, the phase detector operable to generate an error signal according to the relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; and an output divider connected to receive the output from the voltage controlled oscillator to generate a divided output signal, the output divider comprising: a first plurality N of similar transistor stages connected in a divide-by-N sequence, wherein N is an odd integer, the transistor stages configured so that when an output of a last stage is supplied to a first stage in the sequence, the dividing circuit operates as a divide-by-N circuit in which an output signal is generated having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter selectively connectable in a divide-by-M sequence with a second plurality M of transistor stages, wherein M is an even integer, and the second plurality includes at least one of said first plurality of transistor stages, including the first stage, whereby when an output of a last stage in the divide-by-M sequence is supplied to the first stage, the dividing circuit operates as a divide-by-M circuit in which an output signal is generated having one cycle for every M cycles of a clock signal applied to the transistor stages; and a switching circuit having at least two inputs and arranged to selectively connect to the first stage the output of the last stage in either the divide-by-N sequence or the divide-by-M sequence whereby the dividing circuit can be programmed to operate as a divide-by-N or divide-by-M circuit.

Claim 18

A dividing circuit programmable to divide by an N odd integer or an M even integer, comprising: a first plurality of N transistor stages connectable in a divide-by-N sequence, the first plurality of N transistor stages configurable to supply an output of a last transistor stage in the divide-by-N sequence to a first transistor stage in the divide-by-N sequence, a transistor stage in the first plurality of N transistor stages generating a first output signal having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter stage; a second plurality of M transistor stages connectable to the tri-state inverter stage in a divide-by-M sequence, the divide-by-M sequence including at least the first transistor stage in the divide-by-N sequence, the divide-by-M sequence configurable to supply an output of a last stage in the divide-by-M sequence to the first transistor stage in the divide-by-N sequence to generate a second output signal having one cycle for every M cycles of the clock signal; and a switching circuit having a first input connected to the last transistor stage in the divide-by-N sequence and a second input connected to the last stage in the divide-by-M sequence, the switching circuit selectable to connect either the first or second inputs to the first transistor stage in the divide-by-N circuit to respectively program the dividing circuit produce the first or second output signals.

Claim 19

A dividing circuit programmable to divide by an N odd integer or an M even integer, comprising: a first plurality of N transistor stages connectable in a divide-by-N sequence, the first plurality of N transistor stages configurable to supply an output of a last transistor stage in the divide-by-N sequence to a first transistor stage in the divide-by-N sequence, a transistor stage in the first plurality of N transistor stages generating a first output signal having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter stage; a second plurality of M transistor stages connectable to the tri-state inverter stage in a divide-by-M sequence, the divide-by-M sequence including at least the first transistor stage in the divide-by-N sequence, the divide-by-M sequence configurable to supply an output of a last stage in the divide-by-M sequence to the first transistor stage in the divide-by-N sequence to generate a second output signal having one cycle for every M cycles of the clock signal; and a switching circuit having a first input connected to the last transistor stage in the divide-by-N sequence and a second input connected to the last stage in the divide-by-M sequence, the switching circuit selectable to connect either the first or second inputs to the first transistor stage in the divide-by-N circuit to respectively program the dividing circuit produce the first or second output signals.

Claim 20

The dividing circuit of claim 14 wherein the first input of the switching circuit is connected to an output of the (M-p)th stage in the sequence, where p is an odd integer and M-p=N.

Claim 21

The dividing circuit of claim 14 wherein a common sequence of an even number x of transistor stages has an output node connected to first and second circuit branches, the first branch comprising q transistor stages and the second branch comprising r transistor stages and the tri-state inverter stage, with outputs of the first and second branches respectively connected to the first and second inputs of the switching circuit, wherein N=x+q, M=x+r, q is an odd integer greater than or equal to 1, and r is an even integer greater than or equal to zero.

Claim 22

The dividing circuit of claim 16 wherein q=1 and r=0.

Claim 23

The dividing circuit of claim 14 wherein the switching circuit is a multiplexer, the multiplexer having a select input to receive a programming signal to effect the selective connection.

Claim 24

A phase-locked-loop circuit, comprising: a phase detector having a first input for receiving a reference signal and a second input for receiving a feedback signal, the phase detector operable to generate an error signal according to a relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; a feedback divider circuit connected to receive an output from the voltage controlled oscillator and to divide the output by a predetermined integer to generate the feedback signal; and an input divider to divide the reference signal prior to the phase detector, the input divider comprising a dividing circuit programmable to divide by an N odd integer or an M even integer, comprising: a first plurality of N transistor stages connectable in a divide-by-N sequence, the first plurality of N transistor stages configurable to supply an output of a last transistor stage in the divide-by-N sequence to a first transistor stage in the divide-by-N sequence, a transistor stage in the first plurality of N transistor stages generating a first output signal having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter stage; a second plurality of M transistor stages connectable to the tri-state inverter stage in a divide-by-M sequence, the divide-by-M sequence including at least the first transistor stage in the divide-by-N sequence, the divide-by-M sequence configurable to supply an output of a last stage in the divide-by-M sequence to the first transistor stage in the divide-by-N sequence to generate a second output signal having one cycle for every M cycles of the clock signal; a switching circuit having a first input connected to the last transistor stage in the divide-by-N sequence and a second input connected to the last stage in the divide-by-M sequence, the switching circuit selectable to connect either the first or second inputs to the first transistor stage in the divide-by-N circuit to respectively program the dividing circuit produce the first or second output signals.

Claim 25

A phase-locked-loop circuit, comprising: a phase detector having a first input for receiving a reference signal and a second input for receiving a feedback signal, the phase detector operable to generate an error signal according to a relative phase of the reference signal and the feedback signal; a voltage controlled oscillator connected to receive a signal representative of the error signal generated by the phase detector; a feedback divider circuit connected to receive an output from the voltage controlled oscillator and to divide the output by a predetermined integer to generate the feedback signal; and an input divider to divide the reference signal prior to the phase detector, the input divider comprising a dividing circuit programmable to divide by an N odd integer or an M even integer, comprising: a first plurality of N transistor stages connectable in a divide-by-N sequence, the first plurality of N transistor stages configurable to supply an output of a last transistor stage in the divide-by-N sequence to a first transistor stage in the divide-by-N sequence, a transistor stage in the first plurality of N transistor stages generating a first output signal having one cycle for every N cycles of a clock signal applied to the transistor stages; a tri-state inverter stage; a second plurality of M transistor stages connectable to the tri-state inverter stage in a divide-by-M sequence, the divide-by-M sequence including at least the first transistor stage in the divide-by-N sequence, the divide-by-M sequence configurable to supply an output of a last stage in the divide-by-M sequence to the first transistor stage in the divide-by-N sequence to generate a second output signal having one cycle for every M cycles of the clock signal; a switching circuit having a first input connected to the last transistor stage in the divide-by-N sequence and a second input connected to the last stage in the divide-by-M sequence, the switching circuit selectable to connect either the first or second inputs to the first transistor stage in the divide-by-N circuit to respectively program the dividing circuit produce the first or second output signals.

Claim 26

The phase-locked-loop circuit of claim 19, further comprising an output divider connected to receive the output from the voltage controlled oscillator to generate a divided output signal.