Fabrication method of a tantalum pentoxide dielectric layer for a DRAM capacitor

Claim 2

A fabrication method of a dielectric layer for a dynamic random access memory capacitor, comprising the steps of: providing a substrate with a polysilicon storage electrode formed on the substrate; covering the polysilicon storage electrode with a tantalum pentoxide dielectric layer; conducting a remote oxygen plasma treatment on the tantalum pentoxide dielectric layer; and conducting a spike annealing process on the tantalum pentoxide dielectric layer after the remote oxygen plasma treatment is conducted, wherein the spike annealing process is conducted at a higher temperature than the remote oxygen plasma treatment, and a duration of the spike annealing process is short enough to substantially eliminate oxide layer formation on the polysilicon storage electrode of the capacitor.

Claim 3

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 1, wherein the tantalum pentoxide layer is formed by methods including chemical vapor deposition.

Claim 4

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 1, wherein the remote oxygen plasma treatment is conducted at approximately 350 to 500° C. for about 30 to 120 seconds.

Claim 5

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 1, wherein the spike annealing process is conducted at about 1000 to 2000° C. for approximately 1 to 2 seconds, and the temperature is ramped at a rate of approximately 50 to 250° C. per second.

Claim 6

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 4, wherein the spike annealing process is conducted in an oxygen atmosphere.

Claim 7

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 4, wherein the spike annealing process is conducted in a nitrous oxide atmosphere.

Claim 8

A fabrication method of a dielectric layer of a dynamic random access memory capacitor, comprising the steps of: providing a substrate with a polysilicon storage electrode formed on the substrate; covering the polysilicon storage electrode with a tantalum pentoxide dielectric layer; conducting an ultraviolet light-ozone treatment on the tantalum pentoxide dielectric layer; and conducting a spike anneal treatment on the tantalum pentoxide dielectric layer after the ultraviolet-ozone treatment is conducted, wherein the spike annealing process is conducted at a higher temperature than the ultraviolet light-ozone treatment, and a duration of the spike annealing process is short enough to substantially eliminate oxide layer formation on the polysilicon storage electrode of the capacitor.

Claim 9

A fabrication method of a dielectric layer of a dynamic random access memory capacitor, comprising the steps of: providing a substrate with a polysilicon storage electrode formed on the substrate; covering the polysilicon storage electrode with a tantalum pentoxide dielectric layer; conducting an ultraviolet light-ozone treatment on the tantalum pentoxide dielectric layer; and conducting a spike anneal treatment on the tantalum pentoxide dielectric layer after the ultraviolet-ozone treatment is conducted, wherein the spike annealing process is conducted at a higher temperature than the ultraviolet light-ozone treatment, and a duration of the spike annealing process is short enough to substantially eliminate oxide layer formation on the polysilicon storage electrode of the capacitor.

Claim 10

The fabrication method of a dielectric layer of a dynamic random access memory capacitor according to claim 7, wherein the tantalum pentoxide dielectric layer is formed by methods including chemical vapor deposition.

Claim 11

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 7, wherein the ultraviolet light-ozone treatment process is conducted at approximately 300 to 450° C.

Claim 12

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 7, wherein the spike annealing process is conducted at a temperature of about 1000 to 2000° C. for approximately 1 to 2 seconds, and the temperature is ramped at a rate of approximately 50 to 250° C. per second.

Claim 13

The fabrication method of a dielectric layer for a dynamic random access memory capacitor according to claim 10, wherein the spike annealing process is conducted in an oxygen environment.

Claim 14

The fabrication method of a dielectric layer of a dynamic random access memory capacitor according to claim 7, wherein the spike annealing process is conducted in a nitrous oxide environment.