Wafer map analysis aid system, wafer map analyzing method and wafer processing method

Claim 2

A wafer map analysis aid system comprising: observing means for executing inspection or measurement on wafers at plural steps of a semiconductor manufacturing process to which said wafers are subjected, to thereby create plural wafer map data which are image data respectively capable of representing results of said inspection or said measurement at said plural steps on images of said wafers as wafer maps, and for adding, to said plural wafer map data, linkers respectively indicating relation to said plural steps; input means for inputting text data related to said plural steps; storing means for storing said plural wafer map data respectively accompanied with said linkers sent from said observing means and said text data sent from said input means; and image display means capable of displaying images of said text data stored in said storing means on a screen, and capable of fetching a specified part of said plural wafer map data from said storing means in accordance with said linkers to thereby display those images on said screen which said part of wafer map data represent as part of said wafer maps.

Claim 3

The wafer map analysis aid system according to claim 1, wherein each of said linkers includes a file name with a processing date, said file name being inherent in a lot.

Claim 4

The wafer map analysis aid system according to claim 1, wherein said text data includes numerical data, and said image display means displays said numerical data in a graph and visually distinguishably indicates a position or positions of said specified part of said plural wafer map data on said graph.

Claim 5

The wafer map analysis aid system according to claim 1, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said image display means superposes and displays plural images of said part of wafer maps by using said information.

Claim 6

The wafer map analysis aid system according to claim 1, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said image display means superposes an image of said part of wafer maps on an image of mask data and displays them by using said information.

Claim 7

The wafer map analysis aid system according to claim 1, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said image display means superposes an image of said part of wafer maps on an image of a shape simulation and displays them by using said information.

Claim 8

The wafer map analysis aid system according to claim 1, wherein said image display means displays said images which said part of wafer map data represent as said part of said wafer maps on said screen in a predetermined order based on said linkers.

Claim 9

A wafer map analyzing method for analyzing a wafer map displayed as an image on an image display means comprising steps of: executing inspection or measurement on wafers at plural steps of a semiconductor manufacturing process to which said wafers are subjected, to thereby create plural wafer map data which are image data respectively capable of representing results of said inspection or said measurement at said plural steps on images of said wafers as wafer maps, adding, to said plural wafer map data, linkers respectively indicating relation to said plural steps; inputting text data related to said plural steps; storing said plural wafer map data respectively accompanied with said linkers and said inputted text data; and causing said image display means to display images of said stored text data, to fetch a specified part from said stored plural wafer map data in accordance with said linkers, and to thereby display images which said part of wafer map data represent as part of said wafer maps.

Claim 10

A wafer map analyzing method for analyzing a wafer map displayed as an image on an image display means comprising steps of: executing inspection or measurement on wafers at plural steps of a semiconductor manufacturing process to which said wafers are subjected, to thereby create plural wafer map data which are image data respectively capable of representing results of said inspection or said measurement at said plural steps on images of said wafers as wafer maps, adding, to said plural wafer map data, linkers respectively indicating relation to said plural steps; inputting text data related to said plural steps; storing said plural wafer map data respectively accompanied with said linkers and said inputted text data; and causing said image display means to display images of said stored text data, to fetch a specified part from said stored plural wafer map data in accordance with said linkers, and to thereby display images which said part of wafer map data represent as part of said wafer maps.

Claim 11

The wafer map analyzing method according to claim 8, wherein each of said linkers includes a file name with a processing date, said file name being inherent in a lot.

Claim 12

The wafer map analyzing method according to claim 8, wherein said text data includes numerical data, said step of causing said image display means to display images of said stored text data includes a step of: displaying said numerical data in a graph, and said wafer map analyzing method further comprises a step of: causing said image display means to visually distinguishably indicate a position or positions of said specified part of said plural wafer map data on said graph.

Claim 13

The wafer map analyzing method according to claim 8, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said step of causing said image display means to display images which said part of wafer map data represent includes a step of: causing said image display means to superpose and display plural images of said part of wafer maps by using said information.

Claim 14

The wafer map analyzing method according to claim 8, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said step of causing said image display means to display images which said part of wafer map data represent includes a step of: causing said image display means to superpose an image of said part of wafer maps on an image of mask data and display them by using said information.

Claim 15

The wafer map analyzing method according to claim 8, wherein said plural wafer map data include information about absolute coordinates and absolute dimensions of said respective wafer maps, and said step of causing said image display means to display images which said part of wafer map data represent includes a step of: causing said image display means to superpose an image of said part of wafer maps on an image of a shape simulation and display them by using said information.

Claim 16

The wafer map analyzing method according to claim 8, wherein said step of causing said image display means to display images which said part of wafer map data represent as part of said wafer maps includes a step of: causing said image display means to display said images which said part of wafer map data represent as said part of aid wafer maps in a predetermined order based on said linkers.

Claim 17

A wafer processing method, comprising steps of: processing a plurality of first wafers included in a first lot by a predetermined manufacturing line; executing inspection or measurement on said first wafers at plural steps of a semiconductor manufacturing process of said predetermined manufacturing line to which said first wafers are subjected, to thereby create plural wafer map data which are image data respectively capable of representing results of said inspection or said measurement at said plural steps on images of said first wafers as wafer maps, adding, to said plural wafer map data, linkers respectively indicating relation to said plural steps; inputting text data related to said plural steps; storing said plural wafer map data respectively accompanied with said linkers and said inputted text data; causing said image display means to display images of said stored text data, to fetch a specified part from said stored plural wafer map data in accordance with said linkers, and to thereby display images which said part of wafer map data represent as part of said wafer maps; analyzing a processing of said plurality of first wafers by said wafer maps; controlling said predetermined manufacturing line by using an analysis result of said wafer maps; and processing a plurality of second wafers included in a second lot by said predetermined manufacturing line which is controlled.

Claim 18

A wafer processing method, comprising steps of: processing a plurality of first wafers included in a first lot by a predetermined manufacturing line; executing inspection or measurement on said first wafers at plural steps of a semiconductor manufacturing process of said predetermined manufacturing line to which said first wafers are subjected, to thereby create plural wafer map data which are image data respectively capable of representing results of said inspection or said measurement at said plural steps on images of said first wafers as wafer maps, adding, to said plural wafer map data, linkers respectively indicating relation to said plural steps; inputting text data related to said plural steps; storing said plural wafer map data respectively accompanied with said linkers and said inputted text data; causing said image display means to display images of said stored text data, to fetch a specified part from said stored plural wafer map data in accordance with said linkers, and to thereby display images which said part of wafer map data represent as part of said wafer maps; analyzing a processing of said plurality of first wafers by said wafer maps; controlling said predetermined manufacturing line by using an analysis result of said wafer maps; and processing a plurality of second wafers included in a second lot by said predetermined manufacturing line which is controlled.

Claim 19

The wafer processing method according to claim 15, wherein said step of causing said image display means to display images which said part of wafer map data represent as part of said wafer maps includes a step of: causing said image display means to display said images which said part of wafer map data represent as said part of a said wafer maps in a predetermined order based on said linkers.

Claim 22

A method as recited in claim 17, comprising: generating numerical data relating to said map data; automatically displaying said numerical data corresponding to said one piece of said first information based upon said selecting step.

Claim 23

A method as recited in claim 17, comprising: generating electrical characteristics data; generating electrical test data; and automatically displaying electrical characteristics data and electrical test data related to said one piece of said first information.

Claim 24

A method as recited in claim 17, comprising: generating manufacturing trend data; and displaying said trend data with said wafer map data.

Claim 25

A method as recited in claim 17, comprising: generating synthesized wafer map data from said wafer map data; and displaying said synthesized wafer map data with said wafer map data.

Claim 26

A method as recited in claim 17, comprising: generating mask data related to said manufacturing process; and displaying said mask data with said wafer map data.