Single electron MOSFET memory device and method

Claim 2

A memory cell including a MOSFET, the MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate formed on a gate insulator separating the gate from the channel, the gate and the gate insulator formed between the source to the drain; and one or more islands of semiconductor material surrounded by an insulator, each island and surrounding insulator formed in a pore extending into the channel.

Claim 3

The memory cell of claim 1 wherein the gate electrode comprises polycrystalline silicon.

Claim 4

The memory cell of claim 1, further comprising a backgate electrode formed adjacent the channel away from the gate electrode.

Claim 5

The memory cell of claim 3 wherein the gate and backgate electrodes comprise polycrystalline silicon.

Claim 6

The memory cell of claim 4 wherein the channel comprises a body of semiconductor material having a maximum dimension of less than two microns and having a carrier concentration of 10 15 /cubic centimeter or less.

Claim 7

The memory cell of claim 1 wherein the islands comprise a material chosen from a group consisting of: silicon, diamond, silicon carbide and silicon oxycarbide.

Claim 8

The memory cell of claim 1 wherein the semiconductor material comprises p-type silicon.

Claim 9

The memory cell of claim 1 wherein each island and surrounding insulator extends into a pore anodically formed in the channel.

Claim 10

The memory cell of claim 1 wherein each island has a maximum dimension of three nanometers and the surrounding insulator has a thickness of between five and twenty nanometers.

Claim 11

A memory device comprising: row and column addressing and driving circuitry; at least one memory array coupled to the addressing and driving, circuitry, the memory array containing a plurality of memory cells arranged in rows and columns, each of the memory cells including a MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and one or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator formed in a pore extending into the channel.

Claim 12

A memory device comprising: row and column addressing and driving circuitry; at least one memory array coupled to the addressing and driving, circuitry, the memory array containing a plurality of memory cells arranged in rows and columns, each of the memory cells including a MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and one or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator formed in a pore extending into the channel.

Claim 13

The memory device of claim 10, further comprising a backgate electrode formed near the channel and remote from the gate.

Claim 14

The memory device of claim 11 wherein the backgate electrode comprises polycrystalline silicon.

Claim 15

The memory device of claim 10 wherein the gate electrode comprises polycrystalline silicon.

Claim 16

The memory device of claim 10, further comprising a backgate electrode formed near the channel and remote from the gate, wherein the gate and the backgate electrode each comprise polycrystalline silicon.

Claim 17

The memory device of claim 10 wherein the islands comprise a material chosen from a group consisting of: silicon, diamond, silicon carbide and silicon oxycarbide.

Claim 18

The memory device of claim 10 wherein the semiconductor material comprises silicon.

Claim 19

The memory device of claim 10 wherein the islands have a maximum dimension of three nanometers, the surrounding insulator has a thickness of between five and twenty nanometers and each island and surrounding insulator extends into a pore anodically formed in the channel.

Claim 20

A memory device comprising: row and column addressing and driving circuitry; at least one memory array coupled to the addressing and driving circuitry containing a plurality of memory cells arranged in rows and columns, each of the memory array, the memory cells including a MOSFET comprising: a drain coupled to a first end of a channel of semiconductor material; a source coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and one or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator extending into a pore anodically formed in the channel.

Claim 21

A memory device comprising: row and column addressing and driving circuitry; at least one memory array coupled to the addressing and driving circuitry containing a plurality of memory cells arranged in rows and columns, each of the memory array, the memory cells including a MOSFET comprising: a drain coupled to a first end of a channel of semiconductor material; a source coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and one or more islands of conductive material each surrounded by an insulator, each island and surrounding insulator extending into a pore anodically formed in the channel.

Claim 22

The memory device of claim 18 wherein the plurality of memory cells comprise a terabit of memory.

Claim 23

The memory device of claim 18 wherein the plurality of memory cells comprise a gigabit of memory.

Claim 24

The memory device of claim 18 wherein each island has a capacitance of less than ten attoFarads and the surrounding insulator has a thickness of less than twenty nanometers.

Claim 25

The memory device of claim 18 wherein the islands comprise a material chosen from a group consisting of: silicon, diamond, silicon carbide and silicon oxycarbide.

Claim 26

The memory device of claim 18 wherein each island has a maximum dimension of four nanometers.

Claim 27

A computer system comprising: a data and address bus; a central processing unit coupled to the data and address bus; an input device coupled to data and address bus; a display coupled to the data and address bus; and a memory coupled to the central processing unit, the memory including a ROM storing instructions providing an operating system for the central processing unit and including a read-write memory providing temporary storage of data, the read-write memory including integrated circuits each comprising: row and column addressing and driving circuitry; a memory array coupled to the addressing and driving circuitry, the memory array containing a plurality of memory cells arranged in rows and columns each of the memory cells including a MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and at least one island of conductive material surrounded by an insulator, the island and the surrounding insulator extending into a pore anodically formed in the channel.

Claim 28

A computer system comprising: a data and address bus; a central processing unit coupled to the data and address bus; an input device coupled to data and address bus; a display coupled to the data and address bus; and a memory coupled to the central processing unit, the memory including a ROM storing instructions providing an operating system for the central processing unit and including a read-write memory providing temporary storage of data, the read-write memory including integrated circuits each comprising: row and column addressing and driving circuitry; a memory array coupled to the addressing and driving circuitry, the memory array containing a plurality of memory cells arranged in rows and columns each of the memory cells including a MOSFET comprising: a source coupled to a first end of a channel of semiconductor material; a drain coupled to a second end of the channel; a gate insulator formed on the channel between the source to the drain; a gate formed on the gate insulator; and at least one island of conductive material surrounded by an insulator, the island and the surrounding insulator extending into a pore anodically formed in the channel.

Claim 29

The computer of claim 24 wherein the plurality of memory cells comprise a gigabit of memory.

Claim 30

The computer of claim 24 wherein the islands comprise a material chosen from a group consisting of: silicon, diamond, silicon carbide and silicon oxycarbide.

Claim 31

The computer of claim 24 wherein each island has less than ten attoFarads of capacitance and the surrounding insulator comprises silicon dioxide having a thickness of less than twenty nanometers.