Patent US6119048A successfully refreshed from Google Patents.
US6119048A
Expired / Lapsed
US
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Integrated circuit for processing digital signal
Assignee: Sony Corp
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Filing: 1999-01-12
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Granted: 2000-09-12
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Expires: 2019-01-12
Abstract
Abstract A digital signal process of a plurality of functions is enabled by a common hardware constructed on one chip having input terminals t1, t2 and t2'; output terminals t3 and t4; and a control signal input terminal t5. The chip is constructed to include class sorting circuits 111a and 111b; delay and selecting circuits 112a and 112b; switching circuits 113a and 113b; switching circuits 114a and 114b; coefficient memories 115a and 115b; filter operating circuits 116a and 116b; a line delay circuit 117; a product sum operating circuit 118; and a switching circuit 119. Signal flow and circuit functions are selectively controlled by control signals. The functions of the chip can be consequently switched and a plurality of signal processes are realized by one chip.
Inventors
- 👤 Tetsujiro Kondo
- 👤 Takashi Horishi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 10:02
CPC Classifications
G; G06; G06T; G06T1/00; G06F; G06F17/00; G06F17/10; G06T1/20
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
176 words
An integrated circuit for processing a digital signal, in which a plurality of circuit groups and means for enabling at least two states are provided in a single integrated circuit and said enabling means controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit, wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connecting state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state.
Claim 2
Dependent Claim
176 words
An integrated circuit for processing a digital signal, in which a plurality of circuit groups and means for enabling at least two states are provided in a single integrated circuit and said enabling means controlled by a control signal which is indicative of a desired signal processing function to be performed by the integrated circuit and which is supplied from outside the integrated circuit, wherein when said number of selecting devices provided in said single integrated circuit select a first selection state, at least a part of said plurality of circuit groups is set to a first connecting state and is enabled to perform a first signal processing function in said first connection state and, when said number of selecting devices provided in said single integrated circuit select a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state.
Claim 3
Dependent Claim
185 words
An integrated circuit for processing a digital signal, in which a plurality of circuit groups and selecting means which can switch at least two states are provided in a single integrated circuit and said selecting means is selectively controlled by a signal from the outside, characterized in that when said selecting means selects a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said selecting means selects a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state, and at least a part of said plurality of circuit groups is set to have a circuit function which is different in accordance with the selection state of said selecting means, thereby switching the signal processing functions of the whole integrated circuit.
Claim 4
Dependent Claim
185 words
An integrated circuit for processing a digital signal, in which a plurality of circuit groups and selecting means which can switch at least two states are provided in a single integrated circuit and said selecting means is selectively controlled by a signal from the outside, characterized in that when said selecting means selects a first selection state, at least a part of said plurality of circuit groups is set to a first connection state and is enabled to perform a first signal processing function in said first connection state and when said selecting means selects a second selection state, at least a part of said plurality of circuit groups is set to a second connection state different from said first connection state and is enabled to perform a second signal processing function different from said first signal processing function in said connection state, and at least a part of said plurality of circuit groups is set to have a circuit function which is different in accordance with the selection state of said selecting means, thereby switching the signal processing functions of the whole integrated circuit.
Claim 5
Dependent Claim
43 words
An integrated circuit for processing a digital signal according to claim 1 or 2, characterized in that the first signal processing function is a signal process for compensating a resolution and the second signal processing function is a signal process for eliminating noises.
Claim 6
Dependent Claim
86 words
An integrated circuit for processing a digital signal according to claim 2, characterized in that said plurality of circuit groups comprise: first and second filter operating means; means for supplying tap outputs to said first and second filter operating means; means for sorting a class of pixel data which is predicted by said first and second filter operating means, respectively; and a memory for giving filter coefficients to said first and second filter operating means in correspondence to class information from said class sorting means, respectively.
Claim 7
Dependent Claim
47 words
An integrated circuit for processing a digital signal according to claim 4, characterized in that the circuit functions which are different in accordance with the selection state of the selecting means are two of a one-dimensional digital filter, a 2-dimensional digital filter, and a 3-dimensional digital filter.
Claim 8
Dependent Claim
48 words
An integrated circuit for processing a digital signal according to claim 4, characterized in that as a tap output which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional tap output and a two-dimensional tap output.
Claim 9
Dependent Claim
52 words
An integrated circuit for processing a digital signal according to claim 4, characterized in that as a class sorting for generating a coefficient which is given to one of said first and second filter operating means, it is enabled to switch at least a one-dimensional class sorting and a two-dimensional class sorting.
Claim 10
Dependent Claim
145 words
A single integrated circuit for processing a digital signal comprising: a terminal for receiving a digital signal; a control signal terminal for receiving a control signal which is indicative of a desired signal processing function to be performed by the single integrated circuit and which is supplied from outside the single integrated circuit; and a plurality of circuit groups used for performing at least two signal processings in the single integrated circuit wherein when the control signal is indicative of to perform a first signal processing, at least a part of said plurality of circuit groups is enabled to perform the first signal processing function, and when the control signal is indicative of to perform a second signal processing, at least a part of said plurality of circuit groups is enabled to perform the second signal processing function different from said first signal processing function.
Claim 11
Dependent Claim
145 words
A single integrated circuit for processing a digital signal comprising: a terminal for receiving a digital signal; a control signal terminal for receiving a control signal which is indicative of a desired signal processing function to be performed by the single integrated circuit and which is supplied from outside the single integrated circuit; and a plurality of circuit groups used for performing at least two signal processings in the single integrated circuit wherein when the control signal is indicative of to perform a first signal processing, at least a part of said plurality of circuit groups is enabled to perform the first signal processing function, and when the control signal is indicative of to perform a second signal processing, at least a part of said plurality of circuit groups is enabled to perform the second signal processing function different from said first signal processing function.
Claim 12
Dependent Claim
23 words
A single integrated circuit for processing a digital signal according to claim 8, wherein the control signal is independent of the digital signal.
Claim 13
Dependent Claim
24 words
A single integrated circuit for processing a digital signal according to claim 8, wherein at least one signal processing function is classifying adaptive processing.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |