US5027423A
Expired / Lapsed
US
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Image-processing integrated circuit device
Assignee: Fujifilm Business Innovation Corp
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Filing: 1989-07-12
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Granted: 1991-06-25
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Expires: 2009-07-12
Abstract
Abstract An image-processing integrated circuit device comprises a delay circuit and adder group, a multiplication block group, and an adder group. Image data in a window are fed to the delay circuit and adder group simultaneously row by row and then added up for every symmetrical positions in the window. The respective sums of the image data thus added up for every symmetrical positions are multiplied by corresponding coefficient data in the multiplication block group. Lastly, the respective results of multiplication obtained from the multiplication block group are added up by the adder group to thereby obtain a filter output. The delay circuit and adder group, the multiplication block group, and the adder group can be integrated to form one image-processing integrated circuit device. Accordingly, the number of parts is reduced. Further, not only the image data can be fed into the delay circuit and adder group simultaneously but also the multiplication in the multiplication block group can be carried out in parallel and simultaneously by using exclusive multiplication blocks each provided for symmetrical positions in the window. Accordingly, the speed in filtering processing becomes high.
Inventors
- 👤 Tetsuro Kawata
- 👤 Eiri Hashimoto
- 👤 Nobuaki Miyakawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:04
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0202
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
189 words
An image-processing integrated circuit device comprising: delay circuit and adder means for adding up image data in a window for every one of a group of said image data corresponding to coefficient data of the same value; multiplication block means, comprising a plurality of multiplication blocks, for multiplying the results of the additions performed by the delay circuit and adder means for said every group of ones of said image data by a corresponding one of said coefficient data, in which each of said multiplication blocks comprises: a multiplier; a plurality of coefficient data register means for registering coefficient data for every one of a plurality of different filtering characteristics; and first switching means responsive to at least one changeable selection signal, for switching said coefficient data to be fed from said plurality of coefficient data register means to said multiplier, said changeable selection signal being fed to each of said plurality of multipliers of said multiplication blocks simultaneously; and adder means for adding the results of the multiplication for all the groups of said image data obtained from said multiplication block means to thereby obtain a filter output.
Claim 2
Dependent Claim
189 words
An image-processing integrated circuit device comprising: delay circuit and adder means for adding up image data in a window for every one of a group of said image data corresponding to coefficient data of the same value; multiplication block means, comprising a plurality of multiplication blocks, for multiplying the results of the additions performed by the delay circuit and adder means for said every group of ones of said image data by a corresponding one of said coefficient data, in which each of said multiplication blocks comprises: a multiplier; a plurality of coefficient data register means for registering coefficient data for every one of a plurality of different filtering characteristics; and first switching means responsive to at least one changeable selection signal, for switching said coefficient data to be fed from said plurality of coefficient data register means to said multiplier, said changeable selection signal being fed to each of said plurality of multipliers of said multiplication blocks simultaneously; and adder means for adding the results of the multiplication for all the groups of said image data obtained from said multiplication block means to thereby obtain a filter output.
Claim 3
Dependent Claim
167 words
An image processing integrated circuit device according to claim 1, wherein each said plurality of coefficient data register means registers said coefficient data corresponding to one of a plurality of different filtering characteristics after shifting said coefficient data to be registered by a predetermined number of digits so that a first significant digit of said coefficient data to be registered comes to the head of said coefficient data register; and in which each of said multiplication blocks further comprises: a plurality of shift-quantity register means, corresponding to said plurality of coefficient data register means, for registering a number of shift bits equal to the number of digits of shift of said coefficient data in said plurality of coefficient data register means; barrel shifter means provided at the output side of said multiplier, for reversely shifting the digits of the results of multiplication; and second switching means for switching the quantity of shift to be fed from said plurality of shift-quantity register means to said barrel shifter means.
Claim 4
Dependent Claim
133 words
An image-processing integrated circuit device for processing image data comprising: multiplication block means including a plurality of multiplication blocks each for multiplying one of said image data by coefficient data corresponding to said image data; and adder means for adding the results of the multiplications obtained from said multiplication block group to thereby obtain a filter output; wherein each said multiplication blocks includes a multiplier, a plurality of coefficient data register means for registering coefficient data for each of a plurality of different filtering characteristics, and switching means responsive to at least one changeable selection signal, for switching said coefficient data to be fed from said plurality of coefficient data register means to said multiplier, said changeable selection signal being fed to each of said plurality of multipliers of said multiplication block simultaneously.
Claim 5
Dependent Claim
133 words
An image-processing integrated circuit device for processing image data comprising: multiplication block means including a plurality of multiplication blocks each for multiplying one of said image data by coefficient data corresponding to said image data; and adder means for adding the results of the multiplications obtained from said multiplication block group to thereby obtain a filter output; wherein each said multiplication blocks includes a multiplier, a plurality of coefficient data register means for registering coefficient data for each of a plurality of different filtering characteristics, and switching means responsive to at least one changeable selection signal, for switching said coefficient data to be fed from said plurality of coefficient data register means to said multiplier, said changeable selection signal being fed to each of said plurality of multipliers of said multiplication block simultaneously.
Claim 6
Dependent Claim
242 words
In an image-processing integrated circuit device for processing image data comprising a multiplication block group including a plurality of multiplication block means each for multiplying one of said image data by coefficient data corresponding to said image data, and adder means for adding the results of the multiplications obtained from said multiplication block group to thereby obtain a filter output; the improvement comprising each of said multiplication block means comprising: a multiplier, a plurality of coefficient data register means each for registering said coefficient data corresponding to one of a plurality of different filtering characteristics after shifting said coefficient data to be registered by a predetermined number of digits so that a first significant digit of said coefficient data to be registered comes to the head of said coefficient data register means, first switching means for switching the coefficient data to be fed from said plurality of coefficient data register means to said multiplier, a plurality of shift-quantity register means corresponding to said plurality of coefficient data register means, for registering a quantity of shift bits equal to the number of digits of shift of said coefficient data in said plurality of coefficient data register means; barrel shifter means provided at the output side of said multiplier for reversely shifting the digits of the results of multiplication; and second switching means for switching the quantity of shift to be fed from said plurality of shift-quantity register means to said barrel shifter means.
Claim 7
Dependent Claim
242 words
In an image-processing integrated circuit device for processing image data comprising a multiplication block group including a plurality of multiplication block means each for multiplying one of said image data by coefficient data corresponding to said image data, and adder means for adding the results of the multiplications obtained from said multiplication block group to thereby obtain a filter output; the improvement comprising each of said multiplication block means comprising: a multiplier, a plurality of coefficient data register means each for registering said coefficient data corresponding to one of a plurality of different filtering characteristics after shifting said coefficient data to be registered by a predetermined number of digits so that a first significant digit of said coefficient data to be registered comes to the head of said coefficient data register means, first switching means for switching the coefficient data to be fed from said plurality of coefficient data register means to said multiplier, a plurality of shift-quantity register means corresponding to said plurality of coefficient data register means, for registering a quantity of shift bits equal to the number of digits of shift of said coefficient data in said plurality of coefficient data register means; barrel shifter means provided at the output side of said multiplier for reversely shifting the digits of the results of multiplication; and second switching means for switching the quantity of shift to be fed from said plurality of shift-quantity register means to said barrel shifter means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-06-24 | 1994-12-24 | 1995-06-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-06-24 | 1998-12-24 | 1999-06-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-06-24 | 2002-12-24 | 2003-06-25 | $7700.00 | Window Closed / Lapsed |