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Patent US6118181A successfully refreshed from Google Patents.
US6118181A
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System and method for bonding wafers
Assignee: Agilent Technologies Inc
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Filing: 1998-07-29
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Granted: 2000-09-12
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Expires: 2018-07-29
Abstract
Abstract Two wafers are bonded together through an annealing process that maintains temperatures at CMOS compatible levels (i.e., below 500 degrees Celsius). A layer of palladium (Pd) is formed on a first wafer. Preferably an adhesion layer of chromium (Cr) attaches the palladium layer to the first wafer. The palladium layer is engaged with silicon (Si) from a second wafer, and the engaged wafers are annealed to form a palladium-silicide (PdSi) bond between the palladium layer of the first wafer and the silicon of the second wafer. In addition to bonding the first wafer to the second wafer, the palladium-silicon bond may be used to form an electrical connection between the two wafers so that circuits on both wafers may communicate to one another through the palladium-silicon bond.
Inventors
- 👤 Paul P. Merchant
- 👤 Storrs Hoen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:29
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
58 words
A micromachined system, comprising: a first wafer having a contact consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said chromium attached directly to said palladium; and a second wafer having silicon on at least one surface, said silicon bonded with said palladium to form a bond between said first wafer and said second wafer.
Claim 2
Dependent Claim
58 words
A micromachined system, comprising: a first wafer having a contact consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said chromium attached directly to said palladium; and a second wafer having silicon on at least one surface, said silicon bonded with said palladium to form a bond between said first wafer and said second wafer.
Claim 3
Dependent Claim
40 words
The system of claim 1, wherein said first and second wafers include complementary metal-oxide semiconductor (CMOS) circuitry and said bond forms an electrical connection between said CMOS circuitry of said first wafer and said CMOS circuitry of said second wafer.
Claim 4
Dependent Claim
17 words
The system of claim 1, wherein said bond is formed at temperatures less than 500 degrees Celsius.
Claim 5
Independent Claim
126 words
A system, comprising: a first micromachined wafer having a first layer consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said first layer attached directly to said adhesive layer and a second micromachined wafer having a second layer including silicon, said second layer configured to engage said first layer and to form a bond between said first layer and said second layer when said layers are heated to a bonding temperature, wherein said bond between said first layer and said second layer is sufficient to maintain an alignment of said first wafer with respect to said second wafer and wherein said bond is configured to form an electrical connection between circuitry contained in said first wafer and circuitry contained in said second wafer.
Claim 6
Independent Claim
126 words
A system, comprising: a first micromachined wafer having a first layer consisting essentially of palladium and an adhesive layer consisting essentially of chromium, said first layer attached directly to said adhesive layer and a second micromachined wafer having a second layer including silicon, said second layer configured to engage said first layer and to form a bond between said first layer and said second layer when said layers are heated to a bonding temperature, wherein said bond between said first layer and said second layer is sufficient to maintain an alignment of said first wafer with respect to said second wafer and wherein said bond is configured to form an electrical connection between circuitry contained in said first wafer and circuitry contained in said second wafer.
Claim 7
Dependent Claim
28 words
The system of claim 4, wherein said circuitry contained in said first wafer and said circuitry contained in said second wafer are both complementary metal-oxide semiconductor (CMOS) circuitry.
Claim 8
Dependent Claim
25 words
The system of claim 4, wherein said bond between said first layer and said second layer is formed at temperatures less than 500 degrees Celsius.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-09-12 | 2004-03-13 | 2004-09-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-09-12 | 2008-03-13 | 2008-09-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-09-12 | 2012-03-13 | 2012-09-12 | $7700.00 | Window Closed / Lapsed |