Method and apparatus for upscaling video images in a graphics controller chip

Claim 2

A graphics controller integrated circuit for upscaling a source video image to generate an upscaled video image, the source video image being transmitted by a processing unit comprising a plurality of uncompressed scan lines with each scan line comprising a set of pixel data, the graphics controller integrated circuit comprising: an encoder circuit integrated into the graphics controller integrated circuit for receiving a set of uncompressed pixel data for a first scan line of the source video image from the processing unit and generating a compressed data set corresponding to the set of pixel data for the first scan line; a local memory coupled to receive and store the compressed data set; a decoder circuit integrated into the graphics controller integrated circuit for retrieving the compressed data set in the local memory and for decompressing the compressed data set to generate a decompressed pixel data set; and an interpolator integrated into the graphics controller integrated circuit for receiving the decompressed pixel data set and a set of pixel data for a second scan line of the source video, the interpolator interpolating the decompressed pixel data set and the set of pixel data for the second scan line to generate a set of additional pixel data comprised in the upscaled video image.

Claim 3

The graphics controller integrated circuit of claim 1 wherein a display memory is provided for storing the set of uncompressed pixel data for the first scan line and the set of uncompressed pixel data for the second scan line prior to being received by the encoder circuit and the interpolator respectively.

Claim 4

The graphics controller integrated circuit of claim 1 wherein the decoder circuit comprises a DPCM decoder and the encoder circuit comprises a DPCM encoder.

Claim 5

The graphics controller integrated circuit of claim 3 wherein the DPCM encoder compresses the set of pixel data for the first scan line such that resulting compressed data set comprises half the number bits compared to the number of bits in the set of pixel data for the first scan line.

Claim 6

The graphics controller integrated circuit of claim 3 wherein the interpolator comprises a polyphase interpolator.

Claim 7

The graphics controller integrated circuit of claim 3 wherein the DPCM encoder comprises a first adder for receiving uncompressed pixel data and a predicted value, the first adder generating a difference of the uncompressed pixel data and the predicted value; a quantizer for generating the compressed data set by quantizing the difference; a recoverer for generating a recoverer value from the compressed data set; a second adder for adding the recoverer value with the predicted value to generate an output; and a predictor for generating the predicted value as a function of the output of the second adder.

Claim 8

The graphics controller integrated circuit of claim 6 wherein the predictor comprises a set of flip-flops each for storing a bit of the output of the second adder.

Claim 9

The graphics controller integrated circuit of claim 6 further comprising a override circuit to avoid a overload condition in DPCM decoding and encoding.

Claim 10

The graphics controller integrated circuit of claim 8 wherein the override avoids the overload condition by changing a predicted value to correspond to a present pixel data value.

Claim 11

The graphics controller integrated circuit of claim 8 further comprising a video motion block wherein the video motion block comprises the DPCM encoder, the DPCM decoder, the override and the local memory.

Claim 12

The graphics controller integrated circuit of claim 10 further comprising a video controller for sending a set of graphics pixels; and a multiplexor for receiving the graphics pixels and pixel data of the upscaled video image, and for selectively sending to a display unit one of the graphics pixels and pixel data of the upscaled video image.

Claim 13

The graphics controller integrated circuit of claim 11 wherein the encoder circuit receives pixel data of the first scan line from a display memory.

Claim 14

A computer system for displaying a source video image on a display unit, said source video image comprising a plurality of uncompressed scan lines with each scan line comprising a set of pixel data, said computer system comprising: a processing unit for transmitting the source video image comprising a plurality of uncompressed scan lines; a display memory for storing graphics data; a display unit; and a graphics controller integrated circuit receiving the uncompressed pixel data of said source video image from the processing unit and said graphics data, and upscaling said source video image to generate an upscaled video image prior to displaying said graphics and said upscaled source video image on said display unit, said graphics controller circuit comprising: an encoder circuit integrated into the graphics controller integrated circuit for receiving a set of uncompressed pixel data for a first scan line of the source video image and generating a compressed data set corresponding to the set of pixel data for the first scan line; a local memory coupled to receive and store the compressed data set; a decoder circuit integrated into the graphics controller integrated circuit for retrieving the compressed data set in the local memory and for decompressing the compressed data set to generate a decompressed pixel data set; and an interpolator integrated into the graphics controller integrated circuit for receiving the decompressed pixel data set and a set of pixel data for a second scan line of the source video, the interpolator interpolating the decompressed pixel data set and the set of pixel data for the second scan line to generate a set of additional pixel data comprised in the upscaled video image.

Claim 15

A computer system for displaying a source video image on a display unit, said source video image comprising a plurality of uncompressed scan lines with each scan line comprising a set of pixel data, said computer system comprising: a processing unit for transmitting the source video image comprising a plurality of uncompressed scan lines; a display memory for storing graphics data; a display unit; and a graphics controller integrated circuit receiving the uncompressed pixel data of said source video image from the processing unit and said graphics data, and upscaling said source video image to generate an upscaled video image prior to displaying said graphics and said upscaled source video image on said display unit, said graphics controller circuit comprising: an encoder circuit integrated into the graphics controller integrated circuit for receiving a set of uncompressed pixel data for a first scan line of the source video image and generating a compressed data set corresponding to the set of pixel data for the first scan line; a local memory coupled to receive and store the compressed data set; a decoder circuit integrated into the graphics controller integrated circuit for retrieving the compressed data set in the local memory and for decompressing the compressed data set to generate a decompressed pixel data set; and an interpolator integrated into the graphics controller integrated circuit for receiving the decompressed pixel data set and a set of pixel data for a second scan line of the source video, the interpolator interpolating the decompressed pixel data set and the set of pixel data for the second scan line to generate a set of additional pixel data comprised in the upscaled video image.

Claim 16

The computer system of claim 13 wherein the display memory stores the set of pixel data for the first scan line and the set of pixel data for the second scan line.

Claim 17

The computer system of claim 13 wherein the decoder circuit comprises a DPCM decoder and the encoder circuit comprises a DPCM encoder.

Claim 18

The computer system of claim 15 wherein the DPCM encoder compresses the set of pixel data for the first scan line such that resulting compressed data set comprises half the number bits compared to the number of bits in the set of pixel data for the first scan line.

Claim 19

The computer system of claim 15 wherein the interpolator comprises a polyphase interpolator.

Claim 20

The computer system of claim 15 where in the DPCM encoder comprises: a first adder for receiving pixel data and a predicted value, the first adder generating a difference of the pixel data and the predicted value; a quantizer for generating the compressed data set by quantizing the difference; a recoverer for generating a recoverer value from the compressed data set; a second adder for adding the recoverer value with the predicted value to generate an output; and a predictor for generating the predicted value as a function of the output of the second adder.

Claim 21

The computer system of claim 18 wherein the predictor comprises a set of flip-flops each for storing a bit of the output of the second adder.

Claim 22

The computer system of claim 18 further comprising a override to avoid a overload condition in DPCM decoding and encoding.

Claim 23

The computer system of claim 20 wherein the override avoids the overload condition by changing a predicted value to correspond to a present pixel data value.

Claim 24

The computer system of claim 20 further comprising a video motion block wherein the video motion block comprises the DPCM encoder, the DPCM decoder, the override and the local memory.

Claim 25

The computer system of claim 22 further comprising a video controller for sending a set of graphics pixels; and a multiplexor for receiving the graphics pixels and pixel data of the upscaled video image, and for selectively sending to a display unit one of the graphics pixels and pixel data of the upscaled video image.

Claim 28

The method of claim 24 wherein said step of compressing comprises the step of using differential pulse code modulating (DPCM).

Claim 29

The method of claim 25 further comprising the steps of storing said uncompressed source video image in a display memory wherein said step of receiving receives said first uncompressed scan line from said display memory.

Claim 30

The method of claim 26 wherein said step of using DPCM generates said compressed data comprising one half the number of bits compared to number of bits in the pixel data of said uncompressed first scan line in the source video image.

Claim 31

A graphics controller integrated circuit for displaying a source video image on a display unit, said source video image being transmitted by a processing unit comprising a plurality of uncompressed scan lines with each scan line comprising a set of pixel data, said graphics controller integrated circuit comprising: a DPCM encoder circuit integrated into the graphics controller integrated circuit for receiving a set of uncompressed pixel data for a first scan line of said source video image from the processing unit and generating a compressed data set using a DPCM encoding scheme corresponding to the set of pixel data of the first scan line; a local memory coupled to receive and store the compressed data set; a DPCM decoder circuit integrated into the graphics controller integrated circuit for retrieving said compressed data set in said local memory and for decompressing said compressed data set to generate a decompressed pixel data set; an interpolator integrated into the graphics controller integrated circuit for receiving said decompressed pixel data set and a set of pixel data for a second scan line of said source video, said interpolator interpolating the decompressed pixel data set and the set of pixel data for the second scan line to generate a set of additional pixel data comprised in an upscaled image; a video controller for receiving a graphics data from a host, and generating a corresponding pixel data; and a multiplexor for selectively forwarding to said display unit either pixel data corresponding to said graphics data or pixel data of said upscaled image.

Claim 32

A graphics controller integrated circuit for displaying a source video image on a display unit, said source video image being transmitted by a processing unit comprising a plurality of uncompressed scan lines with each scan line comprising a set of pixel data, said graphics controller integrated circuit comprising: a DPCM encoder circuit integrated into the graphics controller integrated circuit for receiving a set of uncompressed pixel data for a first scan line of said source video image from the processing unit and generating a compressed data set using a DPCM encoding scheme corresponding to the set of pixel data of the first scan line; a local memory coupled to receive and store the compressed data set; a DPCM decoder circuit integrated into the graphics controller integrated circuit for retrieving said compressed data set in said local memory and for decompressing said compressed data set to generate a decompressed pixel data set; an interpolator integrated into the graphics controller integrated circuit for receiving said decompressed pixel data set and a set of pixel data for a second scan line of said source video, said interpolator interpolating the decompressed pixel data set and the set of pixel data for the second scan line to generate a set of additional pixel data comprised in an upscaled image; a video controller for receiving a graphics data from a host, and generating a corresponding pixel data; and a multiplexor for selectively forwarding to said display unit either pixel data corresponding to said graphics data or pixel data of said upscaled image.