US5608864A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Variable pixel depth and format for video windows
Assignee: S3 Graphics Co Ltd
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Filing: 1994-04-29
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Granted: 1997-03-04
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Expires: 2014-04-29
Abstract
Abstract A computer video controller, particularly a VGA or SVGA video controller for use with graphical user interface (GUI) software such as WINDOWS™ or OS/2™ is provided with two video data pipelines for simultaneously displaying full motion video within a window in a video display. A first data pipeline displays background video at a first pixel depth. A second data pipeline is provided to display a motion video window at a second, usually higher, pixel depth. The location of the motion video window is measured horizontally in number of memory fetch cycles needed to retrieve the horizontal scan line of pixel data abutting the motion video window. The width of the motion video window is measured in the number of memory fetches required to retrieve one scan line of the motion video window. By providing two parallel data pipelines having equal delays, the motion video window can be generated by selectively retrieving background pixel data or motion video window pixel data and transferring the data to the appropriate pipeline. In an alternative embodiment, data tags may be used to distinguished between background and motion video window pixel data. The controller may also support various compression formats for motion video.
Inventors
- 👤 Rakesh K. Bindlish
- 👤 Vlad Bril
- 👤 Alexander Eglit
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:01
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/14; H; H04; H04N; H04N5/00; H04N5/44; H04N5/445; H04N5/45; G09G2340/00; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 42
Claim 1
Independent Claim
247 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory to retrieve a scan line of said first portion of said image abutting said second portion of said image; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data having pixel depth different from pixel depth of said first pixel data; and control means, coupled to said memory array, said register means, said first FIFO, and said second FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO.
Claim 2
Independent Claim
247 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory to retrieve a scan line of said first portion of said image abutting said second portion of said image; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data having pixel depth different from pixel depth of said first pixel data; and control means, coupled to said memory array, said register means, said first FIFO, and said second FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO.
Claim 3
Dependent Claim
36 words
The apparatus of claim 1, wherein said location data further comprises a vertical start location defined by a number of scan lines of said first portion of said image abutting said second portion of said image.
Claim 4
Dependent Claim
52 words
The apparatus of claim 2, wherein said location data further comprises a vertical end location defined by the sum of a number of scan lines of said first portion of said image abutting said second portion of said image and a number of scan lines of said second portion of said image.
Claim 5
Dependent Claim
37 words
The apparatus of claim 1, wherein said location data further comprises a horizontal width defined by a number of fetches required from said memory array to retrieve one scan line of said second portion of said image.
Claim 6
Dependent Claim
33 words
The apparatus according to claim 1, further comprising: a first serializer, coupled to said first FIFO, for receiving said first pixel data from said first FIFO and serially outputting said first pixel data.
Claim 7
Dependent Claim
33 words
The apparatus according to claim 5, further comprising: a second serializer, coupled to said second FIFO, for receiving said second pixel data from said first FIFO and serially outputting said second pixel data.
Claim 8
Dependent Claim
81 words
The apparatus of claim 6, further comprising: a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data.
Claim 9
Dependent Claim
51 words
The apparatus of claim 7, further comprising: a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals.
Claim 10
Dependent Claim
72 words
The apparatus of claim 8, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals.
Claim 11
Dependent Claim
40 words
The apparatus of claim 8, further comprising: a video display, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating said image including said first portion and said second portion.
Claim 12
Dependent Claim
18 words
The apparatus according to claim 10, wherein said second portion of said image comprises a motion video window.
Claim 13
Dependent Claim
49 words
The apparatus of claim 7, further comprising: a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal.
Claim 14
Dependent Claim
38 words
The apparatus of claim 12, further comprising: a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 15
Dependent Claim
56 words
The apparatus of claim 1 further comprising tag delay means coupled to said single memory controller, for receiving and storing a data tag corresponding to pixel data received by said first FIFO and said second FIFO, said data tag indicating whether data in a memory fetch comprises said first pixel data or said second pixel data.
Claim 16
Independent Claim
254 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said first pixel data and said second pixel data in said memory array; said single memory controller, coupled to said memory array and said register means for selectively fetching data from said memory array and generating a data tag corresponding to each memory fetch, said data tag indicating whether data in a memory fetch comprises first pixel data or second pixel data; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data; tag delay means, coupled to said single memory controller, for receiving and storing a data tag corresponding to pixel data received by said first FIFO and said second FIFO; and output means, coupled to said first FIFO, said second FIFO and said tag delay means, for selectively outputting data from said first FIFO and said second FIFO as indicated by a corresponding data tag stored in said tag delay means.
Claim 17
Independent Claim
254 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said first pixel data and said second pixel data in said memory array; said single memory controller, coupled to said memory array and said register means for selectively fetching data from said memory array and generating a data tag corresponding to each memory fetch, said data tag indicating whether data in a memory fetch comprises first pixel data or second pixel data; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data; tag delay means, coupled to said single memory controller, for receiving and storing a data tag corresponding to pixel data received by said first FIFO and said second FIFO; and output means, coupled to said first FIFO, said second FIFO and said tag delay means, for selectively outputting data from said first FIFO and said second FIFO as indicated by a corresponding data tag stored in said tag delay means.
Claim 18
Dependent Claim
33 words
The apparatus according to claim 15, further comprising: a first serializer, coupled to said first FIFO, for receiving said first pixel data from said first FIFO and serially outputting said first pixel data.
Claim 19
Dependent Claim
33 words
The apparatus according to claim 16, further comprising: a second serializer, coupled to said second FIFO, for receiving said second pixel data from said first FIFO and serially outputting said second pixel data.
Claim 20
Dependent Claim
81 words
The apparatus of claim 17, further comprising: a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data.
Claim 21
Dependent Claim
51 words
The apparatus of claim 18, further comprising: a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals.
Claim 22
Dependent Claim
72 words
The apparatus of claim 19, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals.
Claim 23
Dependent Claim
40 words
The apparatus of claim 20, further comprising: a video display, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating said image including said first portion and said second portion.
Claim 24
Dependent Claim
18 words
The apparatus according to claim 21, wherein said second portion of said image comprises a motion video window.
Claim 25
Dependent Claim
49 words
The apparatus of claim 18, further comprising: a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal.
Claim 26
Dependent Claim
38 words
The apparatus of claim 23, further comprising: a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 27
Dependent Claim
69 words
The apparatus of claim 23, wherein said flat panel display controller is also coupled to said first serializer and said second serializer, and said flat panel display controller selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into flat panel display signals.
Claim 28
Independent Claim
166 words
A method displaying an image including a first portion having a first pixel depth and a second portion having a second pixel depth, comprising the steps of: storing said image as pixel data in a memory array, said image including first pixel data representing the first portion with the first pixel depth, and second pixel data representing the second portion with the second pixel depth different from the first pixel depth; storing location data representing at least the location of said second portion of said image in a register, said location data comprising at least a horizontal location defined by a number of fetches required from the memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; performing a number of fetches as indicated by said horizontal location data, of said first pixel data from the memory array to a first FIFO, and fetching subsequent second pixel data from the memory to a second FIFO.
Claim 29
Independent Claim
166 words
A method displaying an image including a first portion having a first pixel depth and a second portion having a second pixel depth, comprising the steps of: storing said image as pixel data in a memory array, said image including first pixel data representing the first portion with the first pixel depth, and second pixel data representing the second portion with the second pixel depth different from the first pixel depth; storing location data representing at least the location of said second portion of said image in a register, said location data comprising at least a horizontal location defined by a number of fetches required from the memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; performing a number of fetches as indicated by said horizontal location data, of said first pixel data from the memory array to a first FIFO, and fetching subsequent second pixel data from the memory to a second FIFO.
Claim 30
Dependent Claim
640 words
A computer system for generating a display, comprising: a memory array for storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; at least one register for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data having pixel depth different from pixel depth of said first pixel data; a control logic, coupled to said memory array, said at least one register, said first FIFO, and said second FIFO, for receiving said location data, controlling said video memory to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO; a first serializer, coupled to said first FIFO, for receiving said first pixel data from said first FIFO and serially outputting said first pixel data; a second serializer, coupled to said second FIFO, for receiving said second pixel data from said first FIFO and serially outputting said second pixel data; a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data; a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals; a video display output, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating a video display output including said first portion and said second portion; a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal, wherein said flat panel display controller is also coupled to said first serializer and said second serializer, and said flat panel display driver selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into flat panel display signals; and a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 31
Dependent Claim
640 words
A computer system for generating a display, comprising: a memory array for storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; at least one register for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; a first FIFO, coupled to said memory array, for receiving said first pixel data; a second FIFO, coupled to said memory array, for receiving said second pixel data having pixel depth different from pixel depth of said first pixel data; a control logic, coupled to said memory array, said at least one register, said first FIFO, and said second FIFO, for receiving said location data, controlling said video memory to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO; a first serializer, coupled to said first FIFO, for receiving said first pixel data from said first FIFO and serially outputting said first pixel data; a second serializer, coupled to said second FIFO, for receiving said second pixel data from said first FIFO and serially outputting said second pixel data; a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data; a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals; a video display output, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating a video display output including said first portion and said second portion; a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal, wherein said flat panel display controller is also coupled to said first serializer and said second serializer, and said flat panel display driver selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into flat panel display signals; and a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 32
Dependent Claim
36 words
The apparatus of claim 27, wherein said location data further comprises a vertical start location defined by a number of scan lines of said first portion of said image abutting said second portion of said image.
Claim 33
Dependent Claim
37 words
The apparatus of claim 27, wherein said location data further comprises a horizontal width defined by a number of fetches required from said memory array to retrieve one scan line of said second portion of said image.
Claim 34
Dependent Claim
52 words
The apparatus of claim 29, wherein said location data further comprises a vertical end location defined by the sum of a number of scan lines of said first portion of said image abutting said second portion of said image and a number of scan lines of said second portion of said image.
Claim 35
Dependent Claim
18 words
The apparatus according to claim 27, wherein said second portion of said image comprises a motion video window.
Claim 36
Independent Claim
221 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory to retrieve a scan line of said first portion of said image abutting said second portion of said image; a variable depth FIFO, coupled to said memory array, for receiving said first and second pixel data having different pixel depths; and control means, coupled to said memory array, said register means, said FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said FIFO, and fetching subsequent second pixel data from said memory array to said FIFO.
Claim 37
Independent Claim
221 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory to retrieve a scan line of said first portion of said image abutting said second portion of said image; a variable depth FIFO, coupled to said memory array, for receiving said first and second pixel data having different pixel depths; and control means, coupled to said memory array, said register means, said FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said FIFO, and fetching subsequent second pixel data from said memory array to said FIFO.
Claim 38
Independent Claim
227 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said first pixel data and said second pixel data in said memory array; said single memory controller, coupled to said memory array and said register means for selectively fetching data from said memory array and generating a data tag corresponding to each memory fetch, said data tag indicating whether data in a memory fetch comprises first pixel data or second pixel data; a FIFO, coupled to said memory array, for receiving said first and second pixel data; tag delay means, coupled to said single memory controller, for receiving and storing a data tag corresponding to pixel data received by said FIFO; and output means, coupled to said FIFO, and said tag delay means, for selectively outputting data from said FIFO as indicated by a corresponding data tag stored in said tag delay means.
Claim 39
Independent Claim
227 words
An apparatus for generating a display, comprising: a memory array having a single address bus, a single data bus, and a single memory controller, said memory array storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; register means coupled to said single memory controller for storing location data representing a location of said first pixel data and said second pixel data in said memory array; said single memory controller, coupled to said memory array and said register means for selectively fetching data from said memory array and generating a data tag corresponding to each memory fetch, said data tag indicating whether data in a memory fetch comprises first pixel data or second pixel data; a FIFO, coupled to said memory array, for receiving said first and second pixel data; tag delay means, coupled to said single memory controller, for receiving and storing a data tag corresponding to pixel data received by said FIFO; and output means, coupled to said FIFO, and said tag delay means, for selectively outputting data from said FIFO as indicated by a corresponding data tag stored in said tag delay means.
Claim 40
Dependent Claim
617 words
A computer system for generating a display, comprising: a memory array for storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; at least one register for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; a variable depth FIFO, coupled to said memory array, for receiving said first and second pixel data having different pixel depths; a control logic, coupled to said memory array, said at least one register, said first FIFO, and said second FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO; a first serializer, coupled to said FIFO, for receiving said first pixel data from said FIFO and serially outputting said first pixel data; a second serializer, coupled to said FIFO, for receiving said second pixel data from said FIFO and serially outputting said second pixel data; a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data; a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals; a video display output, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating a video display output including said first portion and said second portion; a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal, wherein said flat panel display controller is also coupled to said first serializer and said second serializer, and said flat panel display driver selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into flat panel display signals; and a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 41
Dependent Claim
617 words
A computer system for generating a display, comprising: a memory array for storing an image as pixel data, said image including first pixel data having a first predetermined pixel depth, and second pixel data having a second predetermined pixel depth, said first pixel data representing a first portion of said image and said second pixel data representing a second portion of said image; at least one register for storing location data representing a location of said second portion of said image within said image, said location data comprising at least a horizontal location defined by a number of fetches required from said memory array to retrieve a scan line of said first portion of said image abutting said second portion of said image; a variable depth FIFO, coupled to said memory array, for receiving said first and second pixel data having different pixel depths; a control logic, coupled to said memory array, said at least one register, said first FIFO, and said second FIFO, for receiving said location data, controlling said memory array to perform a number of fetches of first pixel data as indicated by said horizontal location data, from said memory array to said first FIFO, and fetching subsequent second pixel data from said memory array to said second FIFO; a first serializer, coupled to said FIFO, for receiving said first pixel data from said FIFO and serially outputting said first pixel data; a second serializer, coupled to said FIFO, for receiving said second pixel data from said FIFO and serially outputting said second pixel data; a random access memory palette, coupled to said first serializer and said second serializer, for selectively receiving said first or second pixel data from said first serializer and said second serializer, respectively as a memory address of said random access memory palette, and for outputting red, blue, and green pixel data stored in said random access memory palette at the corresponding memory address indicated by said first pixel data and said second pixel data; a digital to analog converter, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into analog red, blue, and green display signals, wherein said digital to analog converter is also coupled to said first serializer and said second serializer, and said digital to analog converter selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into analog red, blue, and green display signals; a video display output, coupled to said digital to analog converter, for receiving said analog red, blue, and green display signals, and for generating a video display output including said first portion and said second portion; a flat panel display controller, coupled to said random access memory palette, for receiving said red, blue, and green pixel data from said random access memory palette and converting said red, blue, and green pixel data into a flat panel display signal, wherein said flat panel display controller is also coupled to said first serializer and said second serializer, and said flat panel display driver selectively receives said first pixel data and said second pixel data from said first serializer and said second serializer, respectively, as red, blue, and green pixel data, and converts said red, blue, and green pixel data into flat panel display signals; and a flat panel display, coupled to said flat panel display controller, for receiving said flat panel display signal, and for generating said image including said first portion and said second portion.
Claim 42
Dependent Claim
51 words
The system of claim 34 further comprising tag delay means coupled to a memory array controller, for receiving and storing a data tag corresponding to pixel data received by said FIFO, said data tag indicating whether data in a memory fetch comprises said first pixel data or said second pixel data.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-03 | 2000-09-02 | 2001-03-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-03 | 2004-09-02 | 2005-03-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-03 | 2008-09-02 | 2009-03-04 | $7700.00 | Window Closed / Lapsed |