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US6107149A
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CMOS semiconductor device comprising graded junctions with reduced junction capacitance
Assignee: Advanced Micro Devices Inc
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Filing: 1999-06-04
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Granted: 2000-08-22
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Expires: 2019-06-04
Abstract
Abstract A CMOS semiconductor device is formed having an N-channel transistor comprising a graded junction with reduced junction capacitance. The graded junction is achieved by forming a second sidewall spacer on the gate electrode, after source/drain implantations, and ion-implanting an N-type impurity with high diffusivity, e.g., P into an A 5 implant, followed by activation annealing.
Inventors
- 👤 David Wu
- 👤 Scott Luning
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:53
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D64/00; H10D64/01; H10D64/021; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/8316; H10D84/85; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/21; H10P30/212; Y; Y10; Y10S; Y10S257/00; Y10S257/917
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
253 words
A method of manufacturing a semiconductor device, which method comprises: forming a dielectric layer on a surface of a semiconductor substrate; forming a conductive layer on the dielectric layer; patterning to form a gate electrode, having side surfaces, on the surface of the semiconductor substrate in an N-channel transistor region with a gate dielectric layer therebetween; using the gate electrode as a mask, ion implanting a first N-type impurity to form a lightly doped drain (N-LDD) implant: forming a first sidewall spacer, having a first width, on the side surfaces of the gate electrode; using the gate electrode and first sidewall spacer as a mask, ion implanting the first N-type impurity to form a moderately or heavily doped source/drain implant in the semiconductor substrate; forming a second sidewall spacer, having a second width, on the first sidewall spacer; using the gate electrode and the first and second sidewall spacers thereon as a mask, implanting a second N-type impurity, different from the first N-type impurity, to form a second N-type impurity implant in the semiconductor substrate; activation annealing to form: an N-LDD region, comprising the first N-type impurity, extending to a first depth below the surface of the semiconductor substrate; a moderately or heavily doped source/drain region, comprising the first N-type impurity, extending to a second depth greater than the first depth; and a region, comprising the second N-type impurity, extending to a third depth greater than the second depth and forming a graded junction extending under the source/drain region, thereby reducing junction capacitance.
Claim 2
Independent Claim
253 words
A method of manufacturing a semiconductor device, which method comprises: forming a dielectric layer on a surface of a semiconductor substrate; forming a conductive layer on the dielectric layer; patterning to form a gate electrode, having side surfaces, on the surface of the semiconductor substrate in an N-channel transistor region with a gate dielectric layer therebetween; using the gate electrode as a mask, ion implanting a first N-type impurity to form a lightly doped drain (N-LDD) implant: forming a first sidewall spacer, having a first width, on the side surfaces of the gate electrode; using the gate electrode and first sidewall spacer as a mask, ion implanting the first N-type impurity to form a moderately or heavily doped source/drain implant in the semiconductor substrate; forming a second sidewall spacer, having a second width, on the first sidewall spacer; using the gate electrode and the first and second sidewall spacers thereon as a mask, implanting a second N-type impurity, different from the first N-type impurity, to form a second N-type impurity implant in the semiconductor substrate; activation annealing to form: an N-LDD region, comprising the first N-type impurity, extending to a first depth below the surface of the semiconductor substrate; a moderately or heavily doped source/drain region, comprising the first N-type impurity, extending to a second depth greater than the first depth; and a region, comprising the second N-type impurity, extending to a third depth greater than the second depth and forming a graded junction extending under the source/drain region, thereby reducing junction capacitance.
Claim 3
Dependent Claim
22 words
The method according to claim 1, wherein the dielectric layer comprises a silicon oxide, and the semiconductor substrate comprises doped monocrystalline silicon.
Claim 4
Dependent Claim
14 words
The method according to claim 2, wherein the gate electrode comprises doped polycrystalline silicon.
Claim 5
Dependent Claim
21 words
The method according to claim 1, wherein the second N-type impurity has a greater diffusion coefficient than the first N-type impurity.
Claim 6
Dependent Claim
20 words
The method according to claim 4, wherein the first N-type impurity comprises arsenic, and the second N-type impurity comprises phosphorous.
Claim 7
Dependent Claim
48 words
The method according to claim 5, comprising ion implanting the first N-type impurity as a dosage of about 1×10 13 atoms cm -2 to about 1×10 14 atoms cm -2 , and at an energy of about 10 KeV to about 40 KeV to form the N-LDD implant.
Claim 8
Dependent Claim
54 words
The method according to claim 6, comprising implanting the first N-type impurity at a dosage of about 5×10 14 atoms cm -2 to about 5×10 15 atoms cm -2 , and at an energy of about 20 KeV to about 60 KeV to form the first N-type impurity moderately or heavily doped source/drain implant.
Claim 9
Dependent Claim
50 words
The method according to claim 7, comprising implanting the second N-type impurity at a dosage of about 1×10 13 atoms cm -2 to about 1×10 14 atoms cm -2 , and at an energy of about 20 KeV to about 40 KeV to form the second N-type impurity doped implant.
Claim 10
Dependent Claim
28 words
The method according to claim 8, comprising activation annealing at a temperature of about 1,000° C. to about 1,200° C. for about 10 seconds to about 60 seconds.
Claim 11
Dependent Claim
32 words
The method according to claim 1, wherein the first and second sidewall spacers comprise a material selected from the group consisting of a silicon oxide, a silicon nitride and a silicon oxynitride.
Claim 12
Dependent Claim
36 words
The method according to claim 1, wherein the first width of the first sidewall spacer is about 150Å to about 200Å; and the second width of the second sidewall spacer is about 700Å to about 1,000Å.
Claim 13
Dependent Claim
35 words
The method according to claim 1, wherein the first depth is about 600Å to about 900Å, the second depth is about 1,000Å to about 1,500Å, and the third depth is about 2,000Å to about 2,500Å.
Claim 14
Dependent Claim
18 words
The method according to claim 1, wherein the first and second sidewall spacers comprises a different insulating material.
References Cited (Backward Citations)
US5583067A
Cited
US5943565A
Cited
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