Patent US2746078A successfully refreshed from Google Patents.
Patent US6107129A successfully refreshed from Google Patents.
US6107129A
Expired / Lapsed
US
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Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
Assignee: GlobalFoundries Inc
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Filing: 1998-03-11
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Granted: 2000-08-22
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Expires: 2018-03-11
Abstract
Abstract An integrated circuit is formed whereby MOS transistor junctions are produced which enhance the overall speed of the integrated circuit. The transistor junctions include multiple implants into the lightly doped drain (LDD) areas of the junction, the source/drain areas of the junction or both the LDD and source/drain areas. The first implant of the multiple implants serves to condition the implant area so that the second and subsequent implants are accurately placed with relatively high concentrations closely below the substrate surface. The resulting junction is therefore one which has relatively high drive strength, low contact resitivity, low source-to-drain parasitic resistance, and relatively low junction capacitance.
Inventors
- 👤 Mark I. Gardner
- 👤 Fred N. Hause
- 👤 H. Jim Fulford, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 19:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/603
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
177 words
A method for forming an integrated circuit, comprising: patterning a gate conductor upon a dielectric covered semiconductor substrate, said gate conductor having opposing sidewall surfaces; using the gate conductor as a mask, implanting a first lightly doped drain (LDD) implant species into a first LDD area within the semiconductor substrate; using the gate conductor as a mask, implanting a second LDD implant species into a second LDD area at a greater concentration and at a shallower depth than the first LDD implant species; subsequently forming a spacer upon each of the opposing sidewall surfaces; using the gate conductor and the spacer as a mask, implanting a first source/drain implant species into a first source/drain area laterally spaced from a sidewall surface of the gate conductor and within the semiconductor substrate; and using the gate conductor and the spacer as a mask, implanting a second source/drain implant species into a second source/drain area laterally spaced from the sidewall surface of the gate conductor at a greater concentration and at a shallower depth than the first source/drain implant species.
Claim 2
Independent Claim
177 words
A method for forming an integrated circuit, comprising: patterning a gate conductor upon a dielectric covered semiconductor substrate, said gate conductor having opposing sidewall surfaces; using the gate conductor as a mask, implanting a first lightly doped drain (LDD) implant species into a first LDD area within the semiconductor substrate; using the gate conductor as a mask, implanting a second LDD implant species into a second LDD area at a greater concentration and at a shallower depth than the first LDD implant species; subsequently forming a spacer upon each of the opposing sidewall surfaces; using the gate conductor and the spacer as a mask, implanting a first source/drain implant species into a first source/drain area laterally spaced from a sidewall surface of the gate conductor and within the semiconductor substrate; and using the gate conductor and the spacer as a mask, implanting a second source/drain implant species into a second source/drain area laterally spaced from the sidewall surface of the gate conductor at a greater concentration and at a shallower depth than the first source/drain implant species.
Claim 3
Dependent Claim
57 words
The method as recited in claim 1, wherein said forming comprises: depositing a spacer material across the patterned said gate conductor; and removing said spacer material from horizontal surfaces at a faster rate than from vertical surfaces; and terminating removing said spacer material prior to removing said spacer material from the vertical surface comprising said sidewall spacer.
Claim 4
Dependent Claim
37 words
The method as recited in claim 1, wherein said implanting a first source/drain implant species and said implanting a second source/drain implant species both comprise implanting species into the semiconductor substrate at approximately the same implant angle.
Claim 5
Dependent Claim
39 words
The method as recited in claim 3, wherein said implanting a first source/drain implant species and said implanting a second source/drain implant species both comprise implanting species into the semiconductor substrate at an acute angle to the semiconductor substrate.
Claim 6
Dependent Claim
17 words
The method as recited in claim 4, wherein the acute angle is between 45 and 83 degrees.
Claim 7
Dependent Claim
33 words
The method as recited in claim 1, wherein said implanting a first source/drain implant species comprises implanting into said semiconductor substrate at a substantially different angle than said implanting a second source/drain species.
Claim 8
Dependent Claim
34 words
The method as recited in claim 1, wherein said implanting a first LDD implant species comprises implanting into said semiconductor substrate at a substantially different angle than said implanting a second LDD implant species.
Claim 9
Dependent Claim
24 words
The method as recited in claim 1, wherein the first source/drain implant species and the second source/drain implant species are the same impurity type.
Claim 10
Dependent Claim
34 words
The method as recited in claim 1, wherein the first source/drain implant species, the second source/drain implant species, the first LDD implant species, and the second LDD implant species are the same impurity type.
Claim 11
Dependent Claim
43 words
The method as recited in claim 1, wherein both said implanting a first source/drain implant species and said implanting second source/drain implant species comprise greater impurity concentrations than said implanting a first LDD implant species and said implanting a second LDD implant species.
Claim 12
Dependent Claim
42 words
The method as recited in claim 1, wherein said implanting a first source/drain implant species and said implanting a second source/drain implant species are performed subsequent to said implanting a first LDD implant species and said implanting a second LDD implant species.
Claim 13
Dependent Claim
44 words
The method as recited in claim 1, wherein said first source/drain area is laterally spaced from the sidewall surface of the gate conductor by approximately a thickness of the spacer, and wherein the spacer is arranged exclusively on sidewall surfaces of the gate conductor.
Claim 14
Independent Claim
155 words
A method for forming an integrated circuit, comprising: implanting a first source/drain implant species into a first source/drain area within a semiconductor substrate and arranged on opposite sides of and laterally spaced from sidewall surfaces of a gate conductor, the gate conductor being arranged above the semiconductor substrate, wherein said implanting a first source/drain implant species partially amorphizes the semiconductor substrate within the first source/drain area; and implanting a second source/drain implant species into a second source/drain area within the semiconductor substrate and arranged on opposite sides of and laterally spaced from the sidewall surfaces of the gate conductor, wherein said implanting a second source/drain implant species comprises a greater impurity concentration and a shallower implant depth than said implanting a first source/drain implant species, and wherein the partially amorphized portion of the semiconductor substrate within the first source/drain area inhibits channeling of the second source/drain species during said implanting a second source/drain implant species.
Claim 15
Independent Claim
155 words
A method for forming an integrated circuit, comprising: implanting a first source/drain implant species into a first source/drain area within a semiconductor substrate and arranged on opposite sides of and laterally spaced from sidewall surfaces of a gate conductor, the gate conductor being arranged above the semiconductor substrate, wherein said implanting a first source/drain implant species partially amorphizes the semiconductor substrate within the first source/drain area; and implanting a second source/drain implant species into a second source/drain area within the semiconductor substrate and arranged on opposite sides of and laterally spaced from the sidewall surfaces of the gate conductor, wherein said implanting a second source/drain implant species comprises a greater impurity concentration and a shallower implant depth than said implanting a first source/drain implant species, and wherein the partially amorphized portion of the semiconductor substrate within the first source/drain area inhibits channeling of the second source/drain species during said implanting a second source/drain implant species.
Claim 16
Dependent Claim
113 words
The method as recited in claim 13, further comprising prior to said implanting a first source/drain implant species and said implanting a second source/drain implant species: implanting a first lightly doped drain (LDD) implant species into a first LDD area within the semiconductor substrate, wherein the first LDD area is closer to the sidewalls surfaces of the gate conductor than the first source/drain area; and implanting a second LDD implant species into a second LDD area at a greater impurity concentration and at a shallower implant depth than the first LDD implant species, wherein the second LDD area is closer to the sidewalls surfaces of the gate conductor than the second source/drain area.
Claim 17
Dependent Claim
38 words
The method as recited in claim 14, wherein the first LDD area comprises a source-side LDD region and a drain-side LDD region, and wherein the drain-side LDD region of the first LDD area extends beneath the gate conductor.
Claim 18
Dependent Claim
29 words
The method as recited in claim 15, wherein the drain-side LDD region of the first LDD area is longer than the source-side LDD region of the first LDD area.
Claim 19
Dependent Claim
25 words
The method as recited in claim 14, wherein said implanting a first LDD implant species partially amorphizes the semiconductor substrate within the first LDD area.
Claim 20
Dependent Claim
26 words
The method as recited in claim 13, wherein said implanting a second source/drain implant species is performed subsequent to said implanting a first source/drain implant species.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-22 | 2004-02-21 | 2004-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-22 | 2008-02-21 | 2008-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-22 | 2012-02-21 | 2012-08-22 | $7700.00 | Window Closed / Lapsed |