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US6101227A
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Detector and method for detecting defects in the magnetic media of a mass storage system
Assignee: SWAYZE W DANIEL JR
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Filing: 1997-04-16
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Granted: 2000-08-08
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Expires: 2017-04-16
Abstract
Abstract A detector and method for detecting defects in the magnetic media of a disk drive mass storage system (30) are provided. The detector may include a viterbi detector (54), having a metric circuit (53) and a trellis circuit (55), for use in a read channel (18) during read operations. Known data is originally written to a sector of the magnetic media of a disk/head assembly (12). The known data includes all binary "ones." The sector of known data is later read during a read operation. During this read operation, the read channel (18) receives an analog signal corresponding to the sector of known data. The metric circuit (53) receives a discrete, equalized signal from a finite impulse response filter (48) and provides a transition signal (56). The transition signal (56) is provided to a control circuitry (11) through a data/parameter path (13) after being placed in parallel format by a deserializer (60). A microprocessor (28) of the control circuitry (11) may process the transition signal (56) and determine which of the bits of the transition signal (56) are different from the original known data. Discrepancies indicate the existence and location of a defect in the magnetic media.
Inventors
- 👤 Kerry C. Glover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 21:50
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/10009; G11B20/10037; G11B20/1816; G11B20/182; H; H04; H04L; H04L25/00; H04L25/02; H04L25/06; H04L25/061; H04L25/063
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
261 words
A detector for providing a transition signal to indicate a defect comprising: a metric circuit operable to receive a discrete, equalized signal and to generate the transition signal in response, the metric circuit operable to provide the transition signal to indicate the defect as an output of the detector; a trellis circuit operable to receive the transition signal to indicate the defect and to perform sequence decoding, the trellis circuit operable to provide a digital data output signal in response; wherein the metric circuit comprises a first adder circuit operable to add a positive threshold value to the discrete, equalized signal and to generate a first sum in response; a second adder circuit operable to add a negative threshold value to the discrete, equalized signal and to generate a second sum in response; a first comparator operable to compare the first sum and a current metric value and to generate a positive transition signal in response; a second comparator operable to compare the second sum and the current metric value and to generate a negative transition signal in response; and a sample/hold circuit operable to receive the positive transition signal and the negative transition signal and to provide the current metric value, the sample/hold circuit operable to update the current metric value with the first sum if the positive transition signal indicates that the first sum is less than the current metric value and to update the current metric value with the second sum if the negative transition signal indicates that the second sum is greater than the current metric value.
Claim 2
Dependent Claim
261 words
A detector for providing a transition signal to indicate a defect comprising: a metric circuit operable to receive a discrete, equalized signal and to generate the transition signal in response, the metric circuit operable to provide the transition signal to indicate the defect as an output of the detector; a trellis circuit operable to receive the transition signal to indicate the defect and to perform sequence decoding, the trellis circuit operable to provide a digital data output signal in response; wherein the metric circuit comprises a first adder circuit operable to add a positive threshold value to the discrete, equalized signal and to generate a first sum in response; a second adder circuit operable to add a negative threshold value to the discrete, equalized signal and to generate a second sum in response; a first comparator operable to compare the first sum and a current metric value and to generate a positive transition signal in response; a second comparator operable to compare the second sum and the current metric value and to generate a negative transition signal in response; and a sample/hold circuit operable to receive the positive transition signal and the negative transition signal and to provide the current metric value, the sample/hold circuit operable to update the current metric value with the first sum if the positive transition signal indicates that the first sum is less than the current metric value and to update the current metric value with the second sum if the negative transition signal indicates that the second sum is greater than the current metric value.
Claim 3
Dependent Claim
23 words
The detector of claim 1 wherein the transition signal to indicate the defect includes the positive transition signal and the negative transition signal.
Claim 4
Dependent Claim
27 words
The detector of claim 1 wherein the positive threshold value and the negative threshold value are programmable values that can be provided over a range of values.
Claim 5
Dependent Claim
335 words
A synchronously sampled data channel comprising: a write channel operable to receive and process a digital data signal during a write operation and to generate a write signal in response; a read channel operable to receive and process a read signal during a read operation, to operate in a normal mode and a defect scan mode, and to generate a digital data output signal in response, the read channel including a detector operable to generate a transition signal as an output; wherein the detector comprises: a metric circuit operable to receive a discrete, equalized signal from the read channel and to generate a transition signal, the metric circuit operable to provide the transition signal as an output; and a trellis circuit operable to receive the transition signal and to perform sequence decoding, the trellis circuit operable to provide the digital data output signal; wherein the metric circuit comprises: a first adder circuit operable to add a positive threshold value to the discrete, equalized signal and to generate a first sum signal in response; a second adder circuit operable to add a negative threshold value to the discrete, equalized signal and to generate a second sum signal in response; a first comparator operable to compare the first sum signal and a current metric value and to generate a positive transition signal in response; a second comparator operable to compare the second sum signal and the current metric value and to generate a negative transition signal in response; and a storage circuit operable to receive the positive transition signal and the negative transition signal and to provide the current metric value, the storage circuit operable to update the current metric value with the first sum signal if the positive transition signal indicates that the first sum signal is less than the current metric value, the storage circuit operable to update the current metric value with the second sum signal if the negative transition signal indicates that the second sum signal is greater than the current metric value.
Claim 6
Dependent Claim
335 words
A synchronously sampled data channel comprising: a write channel operable to receive and process a digital data signal during a write operation and to generate a write signal in response; a read channel operable to receive and process a read signal during a read operation, to operate in a normal mode and a defect scan mode, and to generate a digital data output signal in response, the read channel including a detector operable to generate a transition signal as an output; wherein the detector comprises: a metric circuit operable to receive a discrete, equalized signal from the read channel and to generate a transition signal, the metric circuit operable to provide the transition signal as an output; and a trellis circuit operable to receive the transition signal and to perform sequence decoding, the trellis circuit operable to provide the digital data output signal; wherein the metric circuit comprises: a first adder circuit operable to add a positive threshold value to the discrete, equalized signal and to generate a first sum signal in response; a second adder circuit operable to add a negative threshold value to the discrete, equalized signal and to generate a second sum signal in response; a first comparator operable to compare the first sum signal and a current metric value and to generate a positive transition signal in response; a second comparator operable to compare the second sum signal and the current metric value and to generate a negative transition signal in response; and a storage circuit operable to receive the positive transition signal and the negative transition signal and to provide the current metric value, the storage circuit operable to update the current metric value with the first sum signal if the positive transition signal indicates that the first sum signal is less than the current metric value, the storage circuit operable to update the current metric value with the second sum signal if the negative transition signal indicates that the second sum signal is greater than the current metric value.
References Cited (Backward Citations)
US4509608A
Cited
US4881136A
Cited
US4862464A
Cited
US5448583A
Cited
US5150050A
Cited
US5384560A
Cited
US5341387A
Cited
US5737141A
Cited
US5862157A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-08 | 2004-02-07 | 2004-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-08 | 2008-02-07 | 2008-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-08 | 2012-02-07 | 2012-08-08 | $7700.00 | Window Closed / Lapsed |