US4862464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data error detector for digital modems using trellis coding
Assignee: Rembrandt IP Management LLC
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Filing: 1987-12-30
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Granted: 1989-08-29
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Expires: 2007-12-30
Abstract
Abstract A method and system for data error detection for digital modems using trellis coding makes use of a sixteen traceback Viterbi decoder. One embodiment of the invention comprises a circuit which receives a digital data stream from a communications channel such as a telephone line, passes it through conventional elements including a modem demodulator, adaptive equalizer, and slicer and metric calculation module, and then conducts the output of the calculation module to a parallel combination of a sixteen traceback truncated Viterbi decoder and a sixteen symbol delay line. The parallel outputs of the Viterbi decoder and delay line are conveyed to a "EXCLUSIVE NOR" gate wherein an output of "1" indicates error free data.
Inventors
- 👤 William L. Betts
- 👤 Edward S. Zuranski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 17:24
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/37; H03M13/39; H03M13/41
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
99 words
A data error detector circuit for digital modems comprising: means for receiving an analog signal representative of a digital data stream from a communications channel and for reconstituting said signal in digital form; a parallel combination of a traceback truncated Viterbi decoder and a symbol delay line, said decoder and said symbol delay line being connected to an output of said receiving and reconstituting means; and logic means having inputs from said traceback Viterbi decoder and said symbol delay line and functioning to produce a relatively positive output when error free data is being received from said communications channel.
Claim 2
Dependent Claim
99 words
A data error detector circuit for digital modems comprising: means for receiving an analog signal representative of a digital data stream from a communications channel and for reconstituting said signal in digital form; a parallel combination of a traceback truncated Viterbi decoder and a symbol delay line, said decoder and said symbol delay line being connected to an output of said receiving and reconstituting means; and logic means having inputs from said traceback Viterbi decoder and said symbol delay line and functioning to produce a relatively positive output when error free data is being received from said communications channel.
Claim 3
Dependent Claim
15 words
The data error circuit of claim 1 wherein said logic means comprises an "EXCLUSIVE-NOR" gate.
Claim 4
Dependent Claim
26 words
The data error circuit of claim 1 wherein the number of symbols in the delay line and in the traceback truncated Viterbi decoder are the same.
Claim 5
Dependent Claim
31 words
The data error circuit of claim 1 wherein said receiving and reconstituting means comprises a series connection of a modem demodulator, an adaptive equalizer, and a slicer and metric calculation module.
Claim 6
Dependent Claim
117 words
A data error circuit for digital modems comprising: means for receiving an analog signal representative a digital data stream from a communications channel and for reconstituting said signal in digital form; a first traceback truncated Viterbi decoder connected to an output of said receiving and reconstituting means; a parallel combination of a second traceback truncated Viterbi decoder and a symbol delay line, said second decoder and said symbol delay line being connected to an output of said receiving and reconstituting means; and logic means having inputs from said second traceback Viterbi decoder and said symbol delay line and functioning to produce a positive output when an error occurs in the data being received from said communications channel.
Claim 7
Dependent Claim
117 words
A data error circuit for digital modems comprising: means for receiving an analog signal representative a digital data stream from a communications channel and for reconstituting said signal in digital form; a first traceback truncated Viterbi decoder connected to an output of said receiving and reconstituting means; a parallel combination of a second traceback truncated Viterbi decoder and a symbol delay line, said second decoder and said symbol delay line being connected to an output of said receiving and reconstituting means; and logic means having inputs from said second traceback Viterbi decoder and said symbol delay line and functioning to produce a positive output when an error occurs in the data being received from said communications channel.
Claim 8
Dependent Claim
15 words
The data error circuit of claim 5 wherein said logic means comprises an "EXCLUSIVE-NOR" gate.
Claim 9
Dependent Claim
26 words
The data error circuit of claim 5 wherein the number of symbols in the delay line and in the second traceback Viterbi decoder are the same.
Claim 10
Dependent Claim
31 words
The data error circuit of claim 5 wherein said receiving and constituting means comprises a series connection of a modem demodulator, an adaptive equalizer, and a slicer and metric calculation module.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-28 | 1993-02-27 | 1993-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-28 | 1997-02-27 | 1997-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-28 | 2001-02-27 | 2001-08-29 | $7700.00 | Window Closed / Lapsed |