Method of fabrication of a raised source/drain transistor

Claim 1

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a pad oxide portion within an active area; depositing a polysilicon layer over said silicon semiconductor substrate and over said pad oxide portion; depositing a pad oxide layer over said polysilicon layer; forming shallow isolation trench regions on either side of said active area; removing said pad oxide layer; etching and removing said polysilicon layer over said pad oxide portion leaving polysilicon portions between said pad oxide portion and said shallow isolation trench regions; replacing said pad oxide portion with a gate oxide portion; forming a gate conductor, having exposed side walls, over said gate oxide portion and between said polysilicon portions; forming sidewall spacers on said exposed side walls of said gate conductor; said sidewall spacers contacting said polysilicon portions; forming source/drain regions in said active area under said sidewall spacers and said polysilicon portions; and forming a salicide portion over said gate conductor and salicide portions over said polysilicon portions; whereby said formation of said salicide layers over said polysilicon portions consumes a portion of said polysilicon portions leaving the remainder of said polysilicon portions to form shallow source/drain junctions underneath said polysilicon portion salicide portions.

Claim 2

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a pad oxide portion within an active area; depositing a polysilicon layer over said silicon semiconductor substrate and over said pad oxide portion; depositing a pad oxide layer over said polysilicon layer; forming shallow isolation trench regions on either side of said active area; removing said pad oxide layer; etching and removing said polysilicon layer over said pad oxide portion leaving polysilicon portions between said pad oxide portion and said shallow isolation trench regions; replacing said pad oxide portion with a gate oxide portion; forming a gate conductor, having exposed side walls, over said gate oxide portion and between said polysilicon portions; forming sidewall spacers on said exposed side walls of said gate conductor; said sidewall spacers contacting said polysilicon portions; forming source/drain regions in said active area under said sidewall spacers and said polysilicon portions; and forming a salicide portion over said gate conductor and salicide portions over said polysilicon portions; whereby said formation of said salicide layers over said polysilicon portions consumes a portion of said polysilicon portions leaving the remainder of said polysilicon portions to form shallow source/drain junctions underneath said polysilicon portion salicide portions.

Claim 8

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a patterned pad oxide portion within an active area; depositing a first layer of polysilicon over said silicon semiconductor substrate and said pad oxide portion; depositing a layer of pad oxide over said first polysilicon layer; depositing and patterning a layer of SiN over said pad oxide layer; forming two trenches bracketing said active area; filling said trenches with planarized SiO 2 to form two STIs; removing said patterned SiN layer and said pad oxide layer from said first polysilicon layer; selectively etching and removing said polysilicon layer from said pad oxide portion leaving polysilicon portions in said active area; forming a well within said semiconductor structure within said active area; forming a threshold voltage implant within said semiconductor structure within said active area; forming a punchthrough implant within said semiconductor structure within said active area; removing said pad oxide portion from between said active area polysilicon portions; forming a gate oxide portion between said active area polysilicon portions; depositing and patterning a second layer of polysilicon to form a gate conductor having exposed side walls over said gate oxide portion; forming lightly doped source/drain regions proximate said gate conductor within said semiconductor structure within said active area; depositing and etching a layer of SiN to form sidewall spacers on said exposed side walls of said gate conductor; forming heavy doped source/drain regions within said semiconductor structure within said active areas outward of said sidewall spacers; and forming salicide portions over said gate conductor, and over said source drain regions from a portion of said active area polysilicon portions; whereby said source/drain region salicide portions have shallow junctions thereunder comprised of the remaining active area polysilicon portions.

Claim 9

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a patterned pad oxide portion within an active area; depositing a first layer of polysilicon over said silicon semiconductor substrate and said pad oxide portion; depositing a layer of pad oxide over said first polysilicon layer; depositing and patterning a layer of SiN over said pad oxide layer; forming two trenches bracketing said active area; filling said trenches with planarized SiO 2 to form two STIs; removing said patterned SiN layer and said pad oxide layer from said first polysilicon layer; selectively etching and removing said polysilicon layer from said pad oxide portion leaving polysilicon portions in said active area; forming a well within said semiconductor structure within said active area; forming a threshold voltage implant within said semiconductor structure within said active area; forming a punchthrough implant within said semiconductor structure within said active area; removing said pad oxide portion from between said active area polysilicon portions; forming a gate oxide portion between said active area polysilicon portions; depositing and patterning a second layer of polysilicon to form a gate conductor having exposed side walls over said gate oxide portion; forming lightly doped source/drain regions proximate said gate conductor within said semiconductor structure within said active area; depositing and etching a layer of SiN to form sidewall spacers on said exposed side walls of said gate conductor; forming heavy doped source/drain regions within said semiconductor structure within said active areas outward of said sidewall spacers; and forming salicide portions over said gate conductor, and over said source drain regions from a portion of said active area polysilicon portions; whereby said source/drain region salicide portions have shallow junctions thereunder comprised of the remaining active area polysilicon portions.

Claim 14

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a patterned pad oxide portion from about 100 to 400 Å thick within an active area from about 3000 to 100,000 Å wide; depositing a first layer of polysilicon from about 100 to 1000 Å thick over said silicon semiconductor substrate and said pad oxide portion; depositing a layer of pad oxide from about 100 to 400 Å thick over said first polysilicon layer; depositing and patterning a layer of SiN from about 1000 to 3000 Å thick over said pad oxide layer; forming two trenches from about 1000 to 6000 Å deep bracketing said active area; filling said trenches with planarized SiO 2 to form two STIs; removing said patterned SiN layer and said pad oxide layer from said first polysilicon layer; selectively etching and removing said polysilicon layer from said pad oxide portion leaving polysilicon portions in said active area; forming a well within said semiconductor structure within said active area; forming a threshold voltage implant within said semiconductor structure within said active area; forming a punchthrough implant within said semiconductor structure within said active area; removing said pad oxide portion from between said active area polysilicon portions; forming a gate oxide portion from about 18 to 22 Å thick between said active area polysilicon portions; depositing and patterning a second layer of polysilicon from about 1000 to 4000 Å thick to form a gate conductor having exposed side walls over said gate oxide portion; forming lightly doped source/drain regions proximate said gate conductor within said semiconductor structure within said active area; depositing and etching a layer of SiN to form sidewall spacers having a bottom width from about 200 to 2000 Å on said exposed side walls of said gate conductor; forming heavy doped source/drain regions within said semiconductor structure within said active areas outward of said sidewall spacers and extending from said lightly doped source drains; and forming cobalt salicide portions having a thickness from about 100 to 800 Å thick over said gate conductor, and over said source drain regions from a portion of said active area polysilicon portions; whereby said source/drain region salicide portions have shallow junctions from about 800 to 10,000 Å thick thereunder comprised of the remaining active area polysilicon portions.

Claim 15

A method of fabricating a transistor, comprising the steps of: providing a silicon semiconductor substrate having a patterned pad oxide portion from about 100 to 400 Å thick within an active area from about 3000 to 100,000 Å wide; depositing a first layer of polysilicon from about 100 to 1000 Å thick over said silicon semiconductor substrate and said pad oxide portion; depositing a layer of pad oxide from about 100 to 400 Å thick over said first polysilicon layer; depositing and patterning a layer of SiN from about 1000 to 3000 Å thick over said pad oxide layer; forming two trenches from about 1000 to 6000 Å deep bracketing said active area; filling said trenches with planarized SiO 2 to form two STIs; removing said patterned SiN layer and said pad oxide layer from said first polysilicon layer; selectively etching and removing said polysilicon layer from said pad oxide portion leaving polysilicon portions in said active area; forming a well within said semiconductor structure within said active area; forming a threshold voltage implant within said semiconductor structure within said active area; forming a punchthrough implant within said semiconductor structure within said active area; removing said pad oxide portion from between said active area polysilicon portions; forming a gate oxide portion from about 18 to 22 Å thick between said active area polysilicon portions; depositing and patterning a second layer of polysilicon from about 1000 to 4000 Å thick to form a gate conductor having exposed side walls over said gate oxide portion; forming lightly doped source/drain regions proximate said gate conductor within said semiconductor structure within said active area; depositing and etching a layer of SiN to form sidewall spacers having a bottom width from about 200 to 2000 Å on said exposed side walls of said gate conductor; forming heavy doped source/drain regions within said semiconductor structure within said active areas outward of said sidewall spacers and extending from said lightly doped source drains; and forming cobalt salicide portions having a thickness from about 100 to 800 Å thick over said gate conductor, and over said source drain regions from a portion of said active area polysilicon portions; whereby said source/drain region salicide portions have shallow junctions from about 800 to 10,000 Å thick thereunder comprised of the remaining active area polysilicon portions.