Patent US6099582A successfully refreshed from Google Patents.
US6099582A
Expired / Lapsed
US
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Automatic revision of semiconductor device layout for solving contradiction
Assignee: Fujitsu Semiconductor Ltd
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Filing: 1997-09-03
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Granted: 2000-08-08
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Expires: 2017-09-03
Abstract
Abstract A method of changing layout of a semiconductor device includes: a step of preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; a step of detecting a contradictory area in the physical layout not conforming with predetermined design rule; a step of converting the physical layout into a graphical representation by extracting nodes such as a transistor and a contact and branches interconnecting nodes from the physical layout; a step of solving the contradictory area in the graphical representation by inserting a new vector into a corresponding branch; and a step of converting the final graphical representation into a new physical representation. The method can automatically solve contradictory areas of a physical layout of a semiconductor device.
Inventors
- 👤 Tamae Haruki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:58
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
152 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device to be realized with use of a Levenson type phase shift mask; b) detecting a contradictory area in the layout not conforming with predetermined design rules, said rules including rules for a same phase and rules for a reverse phase; c) converting the physical layout into a graphical representation including: c-1) detecting nodes and branches interconnecting the detected nodes from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; c-2) converting the nodes and the branches into the graphical representation; d) solving the contradictory area in the graphical representation; and e) converting the graphical representation into a new physical representation.
Claim 2
Independent Claim
152 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device to be realized with use of a Levenson type phase shift mask; b) detecting a contradictory area in the layout not conforming with predetermined design rules, said rules including rules for a same phase and rules for a reverse phase; c) converting the physical layout into a graphical representation including: c-1) detecting nodes and branches interconnecting the detected nodes from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; c-2) converting the nodes and the branches into the graphical representation; d) solving the contradictory area in the graphical representation; and e) converting the graphical representation into a new physical representation.
Claim 3
Dependent Claim
21 words
A method of changing layout of a semiconductor device according to claim 1, wherein said step b utilizes the physical layout.
Claim 4
Dependent Claim
21 words
A method of changing layout of a semiconductor device according to claim 1, wherein said step b utilizes the graphical representation.
Claim 5
Dependent Claim
45 words
A method of changing layout of a semiconductor device according to claim 1, wherein said step d comprises: d-1) firstly solving a contradictory area in the nodes of the graphical representation; and d-2) secondly solving a contradictory area in the branches of the graphical representation.
Claim 6
Dependent Claim
33 words
A method of changing layout of a semiconductor device according to claim 4, wherein said step c further comprises: c-3) providing sense information to each branch in accordance with the predetermined design rule.
Claim 7
Dependent Claim
29 words
A method of changing layout of a semiconductor device according to claim 5, wherein said step d-2 includes a step of inserting a vector to one of the branches.
Claim 8
Dependent Claim
29 words
A method of changing layout of a semiconductor device according to claim 5, wherein said step d-2 includes a step of generating a graphical representation from two graphical representations.
Claim 9
Dependent Claim
59 words
A method of changing layout of a semiconductor device according to claim 7, wherein said step of generating a graphical representation from two graphical representations includes a step of dividing each of the two graphical representations at a common portion or position and combining a portion of one graphical representation with a different portion of the other graphical representation.
Claim 10
Dependent Claim
37 words
A method of changing layout of a semiconductor device according to claim 7, wherein said step of generating a graphical representation from two graphical representations includes a step of averaging corresponding branches of the two graphical representations.
Claim 11
Independent Claim
127 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; b) converting the physical layout into a graphical representation including: b-1) detecting nodes and branches interconnecting the detected nodes from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; b-2) converting the nodes and the branches into the graphical representation; c) detecting a contradictory area in the layout not conforming with a predetermined design rule; d) optimizing the layout in the graphical representation; and e) converting the final graphical representation into a new physical representation.
Claim 12
Independent Claim
127 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; b) converting the physical layout into a graphical representation including: b-1) detecting nodes and branches interconnecting the detected nodes from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; b-2) converting the nodes and the branches into the graphical representation; c) detecting a contradictory area in the layout not conforming with a predetermined design rule; d) optimizing the layout in the graphical representation; and e) converting the final graphical representation into a new physical representation.
Claim 13
Dependent Claim
21 words
A method of changing layout of a semiconductor device according to claim 10, wherein said step c utilizes the physical layout.
Claim 14
Dependent Claim
21 words
A method of changing layout of a semiconductor device according to claim 10, wherein said step c utilizes the graphical representation.
Claim 15
Dependent Claim
33 words
A method of changing layout of a semiconductor device according to claim 10, wherein said step b further comprises: b-3) providing sense information to each branch in accordance with the predetermined design rule.
Claim 16
Dependent Claim
23 words
A method of changing layout of a semiconductor device according to claim 10, wherein said step d utilizes evaluation of the graphical representation.
Claim 17
Dependent Claim
28 words
A method of changing layout of a semiconductor device according to claim 14, wherein said step d includes summing error functions of constituent elements of the graphical representation.
Claim 18
Dependent Claim
29 words
A method of changing layout of a semiconductor device according to claim 15, wherein said step d includes a step of generating a graphical representation from two graphical representations.
Claim 19
Dependent Claim
52 words
A method of changing layout of a semiconductor device according to claim 16, wherein said step d further includes a step of dividing each of the two graphical representations at a common portion or position and combining a portion of one graphical representation with a different portion of the other graphical representation.
Claim 20
Dependent Claim
30 words
A method of changing layout of a semiconductor device according to claim 16, wherein said step d further includes a step of averaging corresponding branches of the two graphical representations.
Claim 21
Dependent Claim
26 words
A method of changing a layout of a semiconductor device according to claim 15, wherein said step d includes generating children graphic representations by genetic algorithms.
Claim 22
Independent Claim
133 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; b) converting the physical layout into a graphical representation including: b-1) detecting nodes and branches interconnecting the detected nodes, from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; b-2) converting the nodes and the branches into the graphical representation; c) providing error functions to each constituent element of the graphical representation; d) optimizing the layout in the graphical representation by use of genetic algorithms and sum of error functions; and e) converting the graphical representation into a new physical representation.
Claim 23
Independent Claim
133 words
A method of changing layout of a semiconductor device, comprising the steps of: a) preparing a physical layout representative of a layout of circuit constituents of a semiconductor device; b) converting the physical layout into a graphical representation including: b-1) detecting nodes and branches interconnecting the detected nodes, from the physical layout, where each node represents a circuit element, a contact outside of the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; b-2) converting the nodes and the branches into the graphical representation; c) providing error functions to each constituent element of the graphical representation; d) optimizing the layout in the graphical representation by use of genetic algorithms and sum of error functions; and e) converting the graphical representation into a new physical representation.
Claim 24
Dependent Claim
33 words
A method of changing layout of a semiconductor device according to claim 20, further comprising the step of: f) detecting a contradictory area in the layout not conforming with the predetermined design rule.
Claim 25
Dependent Claim
33 words
A method of changing layout of a semiconductor device according to claim 20, wherein said step b further comprises: b-3) providing sense information to each branch in accordance with the predetermined design rule.
Claim 26
Dependent Claim
29 words
A method of changing layout of a semiconductor device according to claim 22, wherein said step d includes inserting a vector in the graphical representation and renewing error functions.
Claim 27
Dependent Claim
29 words
A method of changing layout of a semiconductor device according to claim 22, wherein said step d includes a step of generating a graphical representation from two graphical representations.
Claim 28
Dependent Claim
52 words
A method of changing layout of a semiconductor device according to claim 24, wherein said step d further includes a step of dividing each of the two graphical representations at a common portion or position and combining a portion of one graphical representation with a different portion of the other graphical representation.
Claim 29
Dependent Claim
30 words
A method of changing layout of a semiconductor device according to claim 24, wherein said step d further includes a step of averaging corresponding branches of the two graphical representations.
Claim 30
Dependent Claim
37 words
A method of changing the layout of a semiconductor device according to claim 20, wherein said step d generates children of graphic representations by the genetic algorithms and keeps those children of smaller sum of error functions.
Claim 31
Independent Claim
111 words
A method of changing the layout of a semiconductor device, comprising: preparing a physical layout of a semiconductor device using a phase shift mask; detecting an area in the physical layout which does not conform with predetermined design rules; converting the physical layout to a graphical layout, including: detecting nodes and branches, the nodes being representative of a circuit element, a contact outside the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; converting the nodes and branches into the graphical layout; optimizing the graphical layout according to the predetermined design rules; and converting the optimized graphical layout into a new physical layout.
Claim 32
Independent Claim
111 words
A method of changing the layout of a semiconductor device, comprising: preparing a physical layout of a semiconductor device using a phase shift mask; detecting an area in the physical layout which does not conform with predetermined design rules; converting the physical layout to a graphical layout, including: detecting nodes and branches, the nodes being representative of a circuit element, a contact outside the circuit element, a branching point of a wiring layer, or a terminal point of a wiring layer; converting the nodes and branches into the graphical layout; optimizing the graphical layout according to the predetermined design rules; and converting the optimized graphical layout into a new physical layout.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-08-08 | 2004-02-07 | 2004-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-08-08 | 2008-02-07 | 2008-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-08-08 | 2012-02-07 | 2012-08-08 | $7700.00 | Window Closed / Lapsed |