US6093938A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stacked die integrated circuit device
Assignee: Intel Corp
•
Filing: 1999-05-25
•
Granted: 2000-07-25
•
Expires: 2019-05-25
Abstract
Abstract A compound die may be formed of two dies each having face and back sides, said dies being connected with said dies in face to face alignment. A radiation communication system may be used to assist in aligning the dies and in providing communications between the two dies. In this way, a composite structure may be produced which has advanced capabilities, a small footprint, and low impedance.
Inventors
- 👤 Ronald K. Minemier
- 👤 Jon M. Dhuse
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:32
CPC Classifications
H; H10; H10W; H10W90/00; H01; H01S; H01S5/00; H01S5/02; H10F; H10F55/00; H10F55/20; H10F55/25; H10W46/00; H10W72/00; H10W72/851; H10W90/20; H10W90/293; G; G02; G02B; G02B6/00; G02B6/24; G02B6/42; G02B6/4201; G02B6/4219; G02B6/4228; G02B6/4232; G02B6/43; H10W46/601; H10W72/071; H10W72/072; H10W72/07221; H10W72/07223; H10W72/075; H10W72/90; H10W72/951; H10W90/701; H10W90/721; H10W90/722
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
46 words
A microprocessor comprising: a first die including a microprocessor core; a second die including a memory for said microprocessor core; and radiation receptors and transmitters on said dies to allow said microprocessor core on said first die to communicate with said memory on the second die.
Claim 2
Dependent Claim
46 words
A microprocessor comprising: a first die including a microprocessor core; a second die including a memory for said microprocessor core; and radiation receptors and transmitters on said dies to allow said microprocessor core on said first die to communicate with said memory on the second die.
Claim 3
Dependent Claim
12 words
The microprocessor of claim 1 wherein said memory is a cache memory.
Claim 4
Dependent Claim
15 words
The microprocessor of claim 2 wherein said cache memory is a level two cache memory.
Claim 5
Dependent Claim
15 words
The microprocessor of claim 1 wherein said dies are joined together using heat activation techniques.
Claim 6
Dependent Claim
14 words
The microprocessor of claim 1 wherein said dies are fixed together in face-to-face abutment.
Claim 7
Dependent Claim
26 words
The microprocessor of claim 5 wherein said first die is larger than the second die such that electrical contacts can be made to said first die.
Claim 8
Dependent Claim
16 words
The microprocessor of claim 5 wherein said receptors and transmitters are in contact with one another.
Claim 9
Dependent Claim
16 words
The microprocessor of claim 1 including contacts for sharing power between the first and second dies.
References Cited (Backward Citations)
US4058821A
Cited
US4100562A
Cited
US5148243A
Cited
US5093879A
Cited
US5401983A
Cited
US5654559A
Cited
US5883395A
Cited
US5753928A
Cited
US5545893A
Cited
US5714772A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-25 | 2004-01-24 | 2004-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-25 | 2008-01-24 | 2008-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-25 | 2012-01-24 | 2012-07-25 | $7700.00 | Window Closed / Lapsed |