US6090679A
Expired / Lapsed
US
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Method for forming a crown capacitor
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-11-30
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Granted: 2000-07-18
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Expires: 2018-11-30
Abstract
Abstract A method for forming a bottom storage node of a crown-shaped DRAM capacitor on a substrate is disclosed. The method comprises the steps of: forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; patterning and etching said second insulating layer, stopping at said barrier layer, to form a trench above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.
Inventors
- 👤 Chine-Gie Lou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:40
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/041; H10D1/042; H10D1/60; H10D1/68; H10D1/692; H10D1/711; H10D1/716; H10D1/712
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
218 words
A method for forming a bottom storage node of a DRAM capacitor on a substrate, the method comprising the steps of forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; patterning and etching said second insulating layer, stopping at said barrier layer, to form a trench above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.
Claim 2
Independent Claim
218 words
A method for forming a bottom storage node of a DRAM capacitor on a substrate, the method comprising the steps of forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; patterning and etching said second insulating layer, stopping at said barrier layer, to form a trench above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.
Claim 3
Dependent Claim
18 words
The method of claim 1, wherein said first insulating layer is formed of TEOS oxide, BPSG, and HTO.
Claim 4
Dependent Claim
14 words
The method of claim 1, wherein said barrier layer is formed of silicon nitride.
Claim 5
Dependent Claim
15 words
The method of claim 1, wherein said second insulating layer is formed of silicon oxide.
Claim 6
Dependent Claim
22 words
The method of claim 1, wherein said middle amorphous silicon layer has a dopant concentration of 5E20 to 1E21 atoms/cm 3 .
Claim 7
Dependent Claim
22 words
The method of claim 1, wherein said bottom amorphous silicon layer has a dopant concentration of 2E20 to 3E20 atoms/cm 3 .
Claim 8
Dependent Claim
34 words
The method of claim 1, wherein said top amorphous silicon layer is 300-600 angstroms thick, said middle amorphous silicon layer is 400-800 angstroms thick, and said bottom amorphous silicon layer is 200-500 angstroms thick.
Claim 9
Dependent Claim
31 words
The method of claim 1, further including the steps of: depositing a third dielectric layer over said bottom storage node; and forming a top storage node over said third dielectric layer.
Claim 10
Independent Claim
241 words
A method for forming a bottom storage node of a DRAM capacitor on a substrate, the method comprising the steps of: forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; forming a trench in said second insulating layer above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench and atop said second insulating layer; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing the portion of said top amorphous silicon layer, said middle amorphous silicon layer, and said bottom amorphous silicon layer atop said second insulating layer; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.
Claim 11
Independent Claim
241 words
A method for forming a bottom storage node of a DRAM capacitor on a substrate, the method comprising the steps of: forming a first insulating layer onto said substrate; forming a barrier layer onto said first insulating layer; patterning and etching said first insulating layer and said barrier layer, and stopping at said substrate, to form a contact opening; forming an amorphous silicon plug into said contact opening; forming a second insulating layer onto said amorphous silicon plug and said barrier layer; forming a trench in said second insulating layer above said amorphous silicon plug; forming a bottom amorphous silicon layer along the bottom and sidewalls of said trench and atop said second insulating layer; forming a middle amorphous silicon layer atop said bottom amorphous silicon layer; forming a top amorphous silicon layer atop said middle amorphous silicon layer, wherein said top amorphous silicon layer is undoped, and wherein said middle amorphous silicon layer and said bottom amorphous silicon layer have different dopant concentrations greater than zero; removing the portion of said top amorphous silicon layer, said middle amorphous silicon layer, and said bottom amorphous silicon layer atop said second insulating layer; removing said second insulating layer; removing said barrier layer to expose a portion of said amorphous silicon plug; and forming a hemispherical grain (HSG) polysilicon layer on surfaces of said top amorphous silicon layer and said bottom amorphous silicon layer and on exposed portion of said amorphous silicon plug.
Claim 12
Dependent Claim
18 words
The method of claim 9, wherein said first insulating layer is formed of TEOS oxide, BPSG, and HTO.
Claim 13
Dependent Claim
14 words
The method of claim 9, wherein said barrier layer is formed of silicon nitride.
Claim 14
Dependent Claim
15 words
The method of claim 9, wherein said second insulating layer is formed of silicon oxide.
Claim 15
Dependent Claim
22 words
The method of claim 9, wherein said middle amorphous silicon layer has a dopant concentration of 5E20 to 1E21 atoms/cm 3 .
Claim 16
Dependent Claim
22 words
The method of claim 9, wherein said bottom amorphous silicon layer has a dopant concentration of 2E20 to 3E20 atoms/cm 3 .
Claim 17
Dependent Claim
34 words
The method of claim 9, wherein said top amorphous silicon layer is 300-600 angstroms thick, said middle amorphous silicon layer is 400-800 angstroms thick, and said bottom amorphous silicon layer is 200-500 angstroms thick.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-18 | 2004-01-17 | 2004-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-18 | 2008-01-17 | 2008-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-18 | 2012-01-17 | 2012-07-18 | $7700.00 | Window Closed / Lapsed |