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US6087968A
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Analog to digital converter comprising an asynchronous sigma delta modulator and decimating digital filter
Assignee: NXP BV
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Filing: 1998-04-14
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Granted: 2000-07-11
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Expires: 2018-04-14
Abstract
Abstract An analog to digital converter comprises an asynchronous sigma-delta modulator generating an asynchronous duty cycle modulated square wave, sampling means to synchronously sample the asynchronous square wave and a decimating digital filter to convert the samples from the sampling means into a desired PCM-format.
Inventors
- 👤 Engel Roza
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:17
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/30; H03M3/39; H03M3/412; H03M3/422; H03M3/43; H03M3/432
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
78 words
An analog to digital converter comprising: an asynchronous sigma-delta modulator coupled to the input of the analog to digital converter for modulating an amplitude of an input signal and comprising a comparator which is not switched by an externally applied clock signal, said asynchronous sigma-delta modulator being configured to generate an asynchronous duty cycle modulated signal as an output; a decimating digital filter; and a clock-controlled sampler coupled between the asynchronous sigma-delta modulator and the decimating digital filter.
Claim 2
Dependent Claim
78 words
An analog to digital converter comprising: an asynchronous sigma-delta modulator coupled to the input of the analog to digital converter for modulating an amplitude of an input signal and comprising a comparator which is not switched by an externally applied clock signal, said asynchronous sigma-delta modulator being configured to generate an asynchronous duty cycle modulated signal as an output; a decimating digital filter; and a clock-controlled sampler coupled between the asynchronous sigma-delta modulator and the decimating digital filter.
Claim 3
Dependent Claim
19 words
The analog to digital converter as claimed in claim 1, wherein the clock controlled sampler comprises a polyphase sampler.
Claim 4
Dependent Claim
57 words
The analog to digital converter as claimed in claim 2, wherein the polyphase sampler comprises a clock controlled string of delay cells for delivering phase shifted sampling pulses, and a plurality of samplers, controlled by the phase shifted sampling pulses, the plurality of samplers simultaneously receiving the asynchronous duty cycle modulated signal of the asynchronous sigma-delta modulator.
Claim 5
Dependent Claim
24 words
The analog to digital converter as claimed in claim 3, further comprising a clock circuit configured to control the delay of the delay cells.
Claim 6
Dependent Claim
19 words
The analog to digital converter as claimed in claim 1, wherein the analog to digital converter comprises CMOS technology.
Claim 7
Dependent Claim
32 words
The analog to digital converter as claimed in claim 1, wherein the analog to digital converter is configured to operate using a supply voltage of less than or equal to three volts.
References Cited (Backward Citations)
US4954824A
Cited
US5274372A
Cited
US5396244A
Cited
US5963160A
Cited
US5504751A
Cited
US5640416A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |