US6087855A
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High performance dynamic multiplexers without clocked NFET
Assignee: International Business Machines Corp
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Filing: 1998-06-15
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Granted: 2000-07-11
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Expires: 2018-06-15
Abstract
Abstract Performance is increased within a dynamic multiplexer by removing the foot device and replacing it with a logic gate (such as an OR, NOR, or NAND gate) receiving the select signals and activating the precharge device within the dynamic multiplexer circuit. With such a configuration, crowbar current is still inhibited.
Inventors
- 👤 Marlin Wayne Frederick, Jr.
- 👤 Donald George Mikan, Jr.
- 👤 Eric Bernard Schorn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 08:44
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
90 words
A multiplexer comprising: circuitry for outputting one of a plurality of received data signals in response to receipt of a plurality of select signals; a precharge device coupled to the circuitry for outputting one of the plurality of received data signals in response to receipt of the plurality of select signals; and a logic gate receiving the plurality of select signals and coupled to the precharge device wherein the precharge device is a FET, and wherein an output of the logic gate is connected to a gate of the FET.
Claim 2
Dependent Claim
90 words
A multiplexer comprising: circuitry for outputting one of a plurality of received data signals in response to receipt of a plurality of select signals; a precharge device coupled to the circuitry for outputting one of the plurality of received data signals in response to receipt of the plurality of select signals; and a logic gate receiving the plurality of select signals and coupled to the precharge device wherein the precharge device is a FET, and wherein an output of the logic gate is connected to a gate of the FET.
Claim 3
Dependent Claim
15 words
The multiplexer as recited in claim 1, wherein the logic gate is an OR gate.
Claim 4
Dependent Claim
16 words
The multiplexer as recited in claim 2, wherein the OR gate also receives a clock signal.
Claim 5
Dependent Claim
14 words
The multiplexer as recited in claim 2, wherein the precharge FET is a PFET.
Claim 6
Dependent Claim
15 words
The multiplexer as recited in claim 1, wherein the logic gate is a NOR gate.
Claim 7
Dependent Claim
14 words
The multiplexer as recited in claim 5, wherein the precharge FET is an NFET.
Claim 8
Dependent Claim
15 words
The multiplexer as recited in claim 1, wherein the logic gate is a NAND gate.
Claim 9
Dependent Claim
16 words
The multiplexer as recited in claim 7, wherein the NAND gate also receives a clock signal.
Claim 10
Dependent Claim
21 words
The multiplexer as recited in claim 8, wherein the NAND gate receives complements of the select signals and the clock signal.
Claim 11
Dependent Claim
17 words
The multiplexer as recited in claim 7, wherein the NAND gate receives complements of the select signals.
Claim 12
Dependent Claim
76 words
A dynamic multiplexer circuit comprising: first and second NFETs coupled in series between a node and ground, wherein the first NFET receives a first select signal at its gate, and wherein the second NFET receives a first data signal at its gate; a FET coupled between a power source and the node; and a logic gate receiving the first select signal, wherein an output of the logic gate is coupled to a gate of the FET.
Claim 13
Dependent Claim
76 words
A dynamic multiplexer circuit comprising: first and second NFETs coupled in series between a node and ground, wherein the first NFET receives a first select signal at its gate, and wherein the second NFET receives a first data signal at its gate; a FET coupled between a power source and the node; and a logic gate receiving the first select signal, wherein an output of the logic gate is coupled to a gate of the FET.
Claim 14
Dependent Claim
46 words
The circuit as recited in claim 11, further comprising: third and fourth NFETs coupled in series between the node and ground, wherein the third NFET receives a second select signal at its gate, and wherein the fourth NFET receives a second data signal at its gate.
Claim 15
Dependent Claim
38 words
The circuit as recited in claim 12, wherein the first select signal operates to output the first data signal from the circuit, and wherein the second select signal operates to output the second data signal from the circuit.
Claim 16
Dependent Claim
17 words
The circuit as recited in claim 12, wherein the logic gate also receives the second select signal.
Claim 17
Dependent Claim
16 words
The circuit as recited in claim 14, wherein the logic gate also receives a clock signal.
Claim 18
Dependent Claim
15 words
The multiplexer as recited in claim 15, wherein the logic gate is a NAND gate.
Claim 19
Dependent Claim
21 words
The multiplexer as recited in claim 16, wherein the NAND gate receives complements of the select signals and the clock signal.
Claim 20
Dependent Claim
15 words
The multiplexer as recited in claim 15, wherein the logic gate is an OR gate.
Claim 21
Dependent Claim
41 words
The circuit as recited in claim 14, further comprising: an inverter having an input connected to the node and having an output connected to an output of the circuit; and a second FET coupled between the power source and the node.
Claim 22
Dependent Claim
22 words
The circuit as recited in claim 19, wherein a gate of the second FET is connected to the output of the circuit.
Claim 23
Dependent Claim
45 words
The circuit as recited in claim 19, further comprising: a first PFET coupled between a second node and the power source; and a fifth NFET coupled between the second node and ground, wherein a gate of the second FET is connected to the second node.
Claim 24
Dependent Claim
15 words
The multiplexer as recited in claim 14, wherein the logic gate is an OR gate.
Claim 25
Dependent Claim
15 words
The multiplexer as recited in claim 14, wherein the logic gate is a NOR gate.
Claim 26
Dependent Claim
13 words
The multiplexer as recited in claim 23, wherein the FET is an NFET.
Claim 27
Dependent Claim
15 words
The multiplexer as recited in claim 14, wherein the logic gate is a NAND gate.
Claim 28
Dependent Claim
17 words
The multiplexer as recited in claim 25, wherein the NAND gate receives complements of the select signals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-07-11 | 2004-01-10 | 2004-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-07-11 | 2008-01-10 | 2008-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-07-11 | 2012-01-10 | 2012-07-11 | $7700.00 | Window Closed / Lapsed |