Patent US6081883A successfully refreshed from Google Patents.
US6081883A
Expired / Lapsed
US
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Processing system with dynamically allocatable buffer memory
Assignee: NetApp Inc
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Filing: 1997-12-05
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Granted: 2000-06-27
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Expires: 2017-12-05
Abstract
Abstract A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks. Upon receiving requests for data from the NP, the FSP checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request. The resulting scalable computer provides higher data availability, faster access to shared data, and reduced administrative costs via data consolidation.
Inventors
- 👤 Paul Popelka
- 👤 Tarun Kumar Tripathy
- 👤 Richard Allen Walter
- 👤 Paul Brian Del Fante
- 👤 Murali Sundaramoorthy Repakula
- 👤 Lakshman Narayanaswamy
- 👤 Donald Wayne Sterk
- 👤 Amod Prabhakar Bodas
- 👤 Leslie Thomas McCutcheon
- 👤 Daniel Murray Jones
- 👤 Peter Kingsley Craft
- 👤 Clive Mathew Philbrick
- 👤 David Allan Higgen
- 👤 Edward John Row
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 12:42
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0813; G06F16/00; G06F16/10
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
94 words
A scalable computer system, comprising: an interconnect bus; a host processor coupled to the interconnect bus; and one or more function-specific processors including network processor, a file processor and a storage processor, the one or more function-specific processors coupled to the interconnect bus for communicating with other processors, each function-specific processor having a buffer memory coupled thereto, the buffer memory having one or more segments which serve as function-specific caches to cache function specific data including network processing data, file processing data and storage processing data, the segments being dynamically allocatable to different processors.
Claim 2
Dependent Claim
94 words
A scalable computer system, comprising: an interconnect bus; a host processor coupled to the interconnect bus; and one or more function-specific processors including network processor, a file processor and a storage processor, the one or more function-specific processors coupled to the interconnect bus for communicating with other processors, each function-specific processor having a buffer memory coupled thereto, the buffer memory having one or more segments which serve as function-specific caches to cache function specific data including network processing data, file processing data and storage processing data, the segments being dynamically allocatable to different processors.
Claim 3
Dependent Claim
47 words
The computer system of claim 1, wherein one of the function-specific processor includes: a network processor coupled to the interconnect bus; one or more network interfaces coupled to the network processor; and a read cache coupled to the network processor for buffering requests from the network interfaces.
Claim 4
Dependent Claim
41 words
The computer system of claim 1, wherein one of said function-specific processor includes: a file processor coupled to the interconnect bus; a storage processor coupled to the file processor; and one or more data storage devices coupled to the storage processor.
Claim 5
Dependent Claim
16 words
The computer system of claim 3, further comprising a metadata cache coupled to the file processor.
Claim 6
Dependent Claim
16 words
The computer system of claim 3, further comprising a write cache coupled to the storage processor.
Claim 7
Dependent Claim
69 words
The computer system of claim 1, wherein one of said function-specific processor includes: a file storage processor (FSP) coupled to the interconnect bus; one or more data storage devices coupled to the FSP, each data storage device having files and associated metadata; a metadata cache coupled to the FSP for buffering the metadata; and a write cache coupled to the FSP for buffering file write operations from the FSP.
Claim 8
Dependent Claim
13 words
The computer system of claim 6, further comprising first and second FSP buses.
Claim 9
Dependent Claim
19 words
The computer system of claim 7, further comprising a bridge coupling the interconnect bus to the first FSP bus.
Claim 10
Dependent Claim
18 words
The computer system of claim 8, further comprising a write buffer coupled to first and second FSP buses.
Claim 11
Dependent Claim
42 words
The computer system of claim 9, wherein the write buffer further comprises: a memory array for buffering writes to the data storage devices; and an exclusive OR engine coupled to the memory array for performing redundant array of inexpensive disk (RAID) operations.
Claim 12
Dependent Claim
17 words
The computer system of claim 1, wherein the interconnect bus is a Scalable Coherent Interface (SCI) bus.
Claim 13
Dependent Claim
36 words
The computer system of claim 1, further comprising one or more network processors and one or more file storage processors, each of the network processors capable of communicating directly with each of the file storage processors.
Claim 14
Dependent Claim
45 words
The computer system of claim 12, further comprising: a data storage device coupled to each file storage processor; and a bridge coupled to the interconnect bus and to the data storage device for forwarding requests from the network processors to the respective data storage device.
Claim 15
Dependent Claim
15 words
The computer system of claim 1, wherein the host computer supports a Unix operating system.
Claim 16
Dependent Claim
15 words
The computer system of claim 1, wherein the host computer supports a Windows-NT operating system.
Claim 17
Dependent Claim
29 words
The computer system of claim 1, wherein the computer system has a big endian processor and a little endian processor, further comprising a bi-endian messaging system for interprocessor communication.
Claim 18
Dependent Claim
195 words
A computer system, comprising: an interconnect bus; a host processor coupled to the interconnect bus; a network processor (NP) coupled to the interconnect bus and sharing a single memory image with other processors, including: one or more network interfaces coupled to the NP; and a buffer memory coupled to the NP for buffering requests from the network interfaces, the buffer memory having one or more segments which are dynamically allocatable to different processors; and a file storage processor (FSP) coupled to the interconnect bus, including: one or more data storage devices coupled to the FSP, each data storage device having files and associated metadata; a metadata cache coupled to the FSP for buffering the metadata, the metadata cache maintaining information on data stored on the NP buffer memory; and a write cache coupled to the FSP for buffering file write operations from the FSP, where the FSP, upon receiving requests for data from the NP, checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request.
Claim 19
Dependent Claim
195 words
A computer system, comprising: an interconnect bus; a host processor coupled to the interconnect bus; a network processor (NP) coupled to the interconnect bus and sharing a single memory image with other processors, including: one or more network interfaces coupled to the NP; and a buffer memory coupled to the NP for buffering requests from the network interfaces, the buffer memory having one or more segments which are dynamically allocatable to different processors; and a file storage processor (FSP) coupled to the interconnect bus, including: one or more data storage devices coupled to the FSP, each data storage device having files and associated metadata; a metadata cache coupled to the FSP for buffering the metadata, the metadata cache maintaining information on data stored on the NP buffer memory; and a write cache coupled to the FSP for buffering file write operations from the FSP, where the FSP, upon receiving requests for data from the NP, checks the metadata cache to see if a copy of the requested data has been cached in the NP buffer and, if the copy exists in the NP buffer, causing the NP with the data to respond to the request.
Claim 20
Dependent Claim
16 words
The computer system of claim 17, wherein the FSP further comprises first and second FSP buses.
Claim 21
Dependent Claim
19 words
The computer system of claim 18, further comprising a bridge coupling the interconnect bus to the first FSP bus.
Claim 22
Dependent Claim
18 words
The computer system of claim 18, further comprising a write buffer coupled to first and second FSP buses.
Claim 23
Dependent Claim
42 words
The computer system of claim 20, wherein the write buffer further comprises: a memory array for buffering writes to the data storage devices; and an exclusive OR engine coupled to the memory array for performing redundant array of inexpensive disk (RAID) operations.
Claim 24
Dependent Claim
16 words
The computer of claim 17, wherein the interconnect bus is a Scalable Coherent Interface (SCI) bus.
Claim 25
Dependent Claim
15 words
The computer system of claim 17, wherein the host computer supports a Unix operating system.
Claim 26
Dependent Claim
15 words
The computer system of claim 17, wherein the host computer supports a Windows-NT operating system.
Claim 27
Dependent Claim
29 words
The computer system of claim 17, wherein the computer system has a big endian processor and a little endian processor, further comprising a bi-endian messaging system for interprocessor communication.
Claim 28
Dependent Claim
34 words
The computer system of claim 17, wherein the FSPs collectively provide a single memory image with a memory management that allows a transfer of authority to another FSP and with distributed data content management.
Claim 29
Dependent Claim
23 words
The computer system of claim 17, wherein the computer system provides a single system image (SSI) to an application or to a client.
Claim 30
Dependent Claim
15 words
The computer system of claim 17, wherein the SSI is used in performing system administration.
Claim 31
Dependent Claim
17 words
The computer system of claim 17, wherein data is transferred between data storage devices without host intervention.
Claim 32
Dependent Claim
18 words
The computer system of claim 17, wherein the computer system continues to operate when the host processor fails.
Claim 33
Dependent Claim
20 words
The computer system of claim 17, wherein the computer system continues to operate when one of the network processors fails.
Claim 34
Dependent Claim
21 words
The computer system of claim 17, wherein the computer system continues to operate when one of the file storage processor fails.
Claim 35
Dependent Claim
31 words
The computer system of claim 17, wherein the network processor and the file storage processor are mounted on a single board with a shared cache coherent memory and shared I/O device.
Claim 36
Dependent Claim
14 words
The computer system of claim 32, wherein the FSP controls the NP buffer memory.
Claim 37
Dependent Claim
17 words
The computer system of claim 17, wherein the interconnect bus is an expansion bus on a board.
Claim 38
Dependent Claim
19 words
The computer system of claim 17, wherein each of the NP has a mount table for FSP routing purposes.
Claim 39
Dependent Claim
24 words
The computer system of claim 17, wherein the NP examines the request and directly forward the request to a server based on predetermined criteria.
Claim 40
Dependent Claim
26 words
The computer system of claim 17, wherein the host processor accesses the data storage devices on the FSP as being virtually connected to the host processor.
Claim 41
Dependent Claim
24 words
The computer system of claim 17, further comprising a user application, wherein the application may directly access the data storage device of the FSP.
Claim 42
Independent Claim
210 words
A method for operating scalable computer system having an interconnect bus; a host processor coupled to the interconnect bus; a network processor (NP) coupled to the interconnect bus and sharing a single memory image with other processors, each NP having one or more network interfaces coupled to the NP and a buffer memory coupled to the NP for buffering requests from the network interfaces, the buffer memory having one or more segments which are dynamically allocatable to different processors; and a file storage processor (FSP) coupled to the interconnect bus with one or more data storage devices coupled to the FSP, each data storage device having files and associated metadata, a metadata cache coupled to the FSP for buffering the metadata, the metadata cache maintaining information on data stored on the NP buffer memory, and a write cache coupled to the FSP for buffering file write operations from the FSP, comprising: receiving a data request from the NP; checking the metadata cache to see if a copy of the requested data is cached in the NP buffer; and if the copy exists in the NP buffer, transmitting the copy from the NP buffer in response to the request and otherwise accessing the data storage device in accordance with the request.
Claim 43
Independent Claim
210 words
A method for operating scalable computer system having an interconnect bus; a host processor coupled to the interconnect bus; a network processor (NP) coupled to the interconnect bus and sharing a single memory image with other processors, each NP having one or more network interfaces coupled to the NP and a buffer memory coupled to the NP for buffering requests from the network interfaces, the buffer memory having one or more segments which are dynamically allocatable to different processors; and a file storage processor (FSP) coupled to the interconnect bus with one or more data storage devices coupled to the FSP, each data storage device having files and associated metadata, a metadata cache coupled to the FSP for buffering the metadata, the metadata cache maintaining information on data stored on the NP buffer memory, and a write cache coupled to the FSP for buffering file write operations from the FSP, comprising: receiving a data request from the NP; checking the metadata cache to see if a copy of the requested data is cached in the NP buffer; and if the copy exists in the NP buffer, transmitting the copy from the NP buffer in response to the request and otherwise accessing the data storage device in accordance with the request.
Claim 44
Dependent Claim
44 words
The method of claim 39, wherein the data request arrives at a first NP and wherein the copy of the requested data exists in the buffer of a second NP, further comprising the step of instructing the second NP to respond to the request.
Claim 45
Dependent Claim
30 words
The method of claim 39, further comprising the step of storing data in a bi-endian format in the host processor to minimize conversions between big and little endian data types.
Claim 46
Independent Claim
118 words
A method for operating a scalable computer system having an interconnect bus, a host processor coupled to the interconnect bus, and one or more function-specific processors coupled to the interconnect bus for communicating with other processors, each function-specific processor having a buffer memory coupled thereto, the buffer memory having one or more segments which serve as function-specific caches and which are dynamically allocatable to different processors, comprising: receiving a data request; checking if a copy of the requested data is cached in one of the function-specific processor; and if the copy exists in one of the function-specific processor, transmitting the copy in response to the request and otherwise accessing the data storage device in accordance with the request.
Claim 47
Independent Claim
118 words
A method for operating a scalable computer system having an interconnect bus, a host processor coupled to the interconnect bus, and one or more function-specific processors coupled to the interconnect bus for communicating with other processors, each function-specific processor having a buffer memory coupled thereto, the buffer memory having one or more segments which serve as function-specific caches and which are dynamically allocatable to different processors, comprising: receiving a data request; checking if a copy of the requested data is cached in one of the function-specific processor; and if the copy exists in one of the function-specific processor, transmitting the copy in response to the request and otherwise accessing the data storage device in accordance with the request.
Claim 48
Dependent Claim
44 words
The method of claim 42, wherein the data request arrives at a first function-specific processor and wherein the copy of the requested data exists in a second function specific processor, further comprising the step of instructing the second processor to respond to the request.
Claim 49
Dependent Claim
30 words
The method of claim 42, further comprising the step of storing data in a bi-endian format in the host processor to minimize conversions between big and little endian data types.
References Cited (Backward Citations)
US5163131A
Cited
US5355453A
Cited
US5802366A
Cited
US5931918A
Cited
US5303362A
Cited
US5701516A
Cited
US5611049A
Cited
US5819292A
Cited
US5907689A
Cited
US5941969A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |