US5907689A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Master-target based arbitration priority
Assignee: Hewlett Packard Enterprise Development LP
•
Filing: 1996-12-31
•
Granted: 1999-05-25
•
Expires: 2016-12-31
Abstract
Abstract A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). The SMC includes the main arbitration unit for the PCI bus and also includes the arbiter for the system management local bus. The SMM includes a video controller and/or keyboard and mouse controller connected to the system management local bus to support remote consoling of the SMM. The SMC includes logic to monitor PCI cycles and to issue error signals in the event of a system error. The SMC also isolates failed components by masking request, grant and interrupt lines for the failed device. Further, if a spare component is provided, the SMC permits dynamic switching to the spare. In addition to detecting errors and performing survival and maintenance operations, the SMC enhances system performance during normal operations by supporting master-target priority determinations to more efficiently arbitrate mastership of system busses such as the PCI bus.
Inventors
- 👤 Siamak Tavallaei
- 👤 Gary B. Kotzur
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:03
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/362
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
140 words
A computer system, comprising: a host processor connected to a host bus; a memory controller coupled to said host bus, said memory controller connected to a host memory to control transactions to said host memory; a bus bridge interfacing the host bus to a system bus; a plurality of bus master devices connected to said system bus; a plurality of targets connected to said system bus; a system bus arbitration unit for controlling mastership of said system bus; a register associated with said arbitration unit for assigning priority to certain master-target combinations; wherein said bus arbitration unit receives mastership requests from said bus master devices, and said arbitration unit awards priority to a current master if the current master-target combination has been assigned priority in said register and if the current master is again requesting mastership of the system bus.
Claim 2
Dependent Claim
140 words
A computer system, comprising: a host processor connected to a host bus; a memory controller coupled to said host bus, said memory controller connected to a host memory to control transactions to said host memory; a bus bridge interfacing the host bus to a system bus; a plurality of bus master devices connected to said system bus; a plurality of targets connected to said system bus; a system bus arbitration unit for controlling mastership of said system bus; a register associated with said arbitration unit for assigning priority to certain master-target combinations; wherein said bus arbitration unit receives mastership requests from said bus master devices, and said arbitration unit awards priority to a current master if the current master-target combination has been assigned priority in said register and if the current master is again requesting mastership of the system bus.
Claim 3
Dependent Claim
18 words
A system as in claim 1, wherein the arbitration unit and register reside in a system management module.
Claim 4
Dependent Claim
14 words
A system as in claim 2, wherein the system bus comprises a PCI bus.
Claim 5
Dependent Claim
16 words
A system as in claim 3, wherein the priority master-target combinations are programmed into said register.
Claim 6
Dependent Claim
27 words
A system as in claim 4, wherein the system management module includes a system management processor connected to said arbitration unit through a system management local bus.
Claim 7
Dependent Claim
21 words
A system as in claim 5, wherein the arbitration unit and associated register forms part of a system management interface unit.
Claim 8
Dependent Claim
20 words
A system as in claim 6, wherein the system management interface unit includes registers for storing information regarding pending cycles.
Claim 9
Independent Claim
67 words
A method for granting mastership requests for a system bus, comprising: receiving a mastership request from a system bus master; granting the mastership request to the system bus master; identifying the target of the system bus master; determining if the master-target combination is a priority transaction; assigning priority to the system bus master in the event the system bus master requests further mastership of the system bus.
Claim 10
Independent Claim
67 words
A method for granting mastership requests for a system bus, comprising: receiving a mastership request from a system bus master; granting the mastership request to the system bus master; identifying the target of the system bus master; determining if the master-target combination is a priority transaction; assigning priority to the system bus master in the event the system bus master requests further mastership of the system bus.
Claim 11
Dependent Claim
26 words
A method as in claim 8, wherein the step of granting the mastership request is made on the basis of a pre-assigned priority ranking of masters.
Claim 12
Dependent Claim
18 words
A method as in claim 8, wherein the priority transactions are programmed into the system during system initialization.
Claim 13
Independent Claim
111 words
A method for granting mastership requests for a system bus, comprising: receiving a mastership request during the current arbitration cycle from a system bus master; granting the mastership request during the current arbitration cycle to the system bus master; identifying the target of the system bus master, wherein granting the mastership request is based upon a round-robin methodology; determining if the master-target combination formed by the system bus master and the target is a priority transaction; and assigning priority to the system bus master in the event the system bus master requests mastership of the system bus during the next arbitration cycle and if the master-target combination is a priority transaction.
Claim 14
Independent Claim
111 words
A method for granting mastership requests for a system bus, comprising: receiving a mastership request during the current arbitration cycle from a system bus master; granting the mastership request during the current arbitration cycle to the system bus master; identifying the target of the system bus master, wherein granting the mastership request is based upon a round-robin methodology; determining if the master-target combination formed by the system bus master and the target is a priority transaction; and assigning priority to the system bus master in the event the system bus master requests mastership of the system bus during the next arbitration cycle and if the master-target combination is a priority transaction.
Claim 15
Dependent Claim
120 words
A network server system, comprising: a host processor connected to a host bus; a PCI bus bridge interfacing the host bus to a PCI bus; a system management module connected to said PCI bus, said system management module including a system management processor, a system management control interface unit and a priority register; said system management control interface unit including arbitration logic which operates as the arbitrator for the PCI bus; a plurality of PCI bus master devices connected to the PCI bus; a plurality of targets on the PCI bus; wherein the priority register has stored therein priority master-target combinations; and said arbitration logic awards priority based in part on the priority master-target combination stored in said priority register.
Claim 16
Dependent Claim
120 words
A network server system, comprising: a host processor connected to a host bus; a PCI bus bridge interfacing the host bus to a PCI bus; a system management module connected to said PCI bus, said system management module including a system management processor, a system management control interface unit and a priority register; said system management control interface unit including arbitration logic which operates as the arbitrator for the PCI bus; a plurality of PCI bus master devices connected to the PCI bus; a plurality of targets on the PCI bus; wherein the priority register has stored therein priority master-target combinations; and said arbitration logic awards priority based in part on the priority master-target combination stored in said priority register.
Claim 17
Dependent Claim
23 words
A server system as in claim 12, wherein said arbitration logic monitors a target of a current transaction after awarding a mastership requests.
Claim 18
Dependent Claim
27 words
A system as in claim 13, wherein said arbitration logic identifies and stores a value representing a master that is currently granted mastership of the PCI bus.
Claim 19
Dependent Claim
23 words
A system as in claim 14, wherein said arbitration logic compares the master-target combination to priority master-target combinations stored in the priority registers.
Claim 20
Dependent Claim
25 words
A system as in claim 15, wherein the arbitration logic gives priority to a current master if the current master-target combination is a priority combination.
References Cited (Backward Citations)
US5247620A
Cited
US5434983A
Cited
US5469577A
Cited
US5564025A
Cited
US5450551A
Cited
US5596729A
Cited
US5740387A
Cited
US5761452A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-05-24 | 2002-11-23 | 2003-05-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-05-24 | 2006-11-23 | 2007-05-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-05-24 | 2010-11-23 | 2011-05-25 | $7700.00 | Window Closed / Lapsed |