Patent US6081572A successfully refreshed from Google Patents.
US6081572A
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Lock-in aid frequency detector
Assignee: Maxim Integrated Products Inc
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Filing: 1998-08-27
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Granted: 2000-06-27
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Expires: 2018-08-27
Abstract
Abstract Circuit and method for generating a signal for use in locking a second signal on a first signal. The first and second signals have an associated frequency. A first beat note signal and a second beat note signal are generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal. The circuit includes a first and second flip-flop and detector circuitry. The first flip-flop is configured to receive the first and second beat note signals for generating a first state signal. The first flip-flop generates the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal. The second flip-flop is configured to receive the first and second beat note signals for generating a second state signal. The second flip-flop generates the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal. The detector circuitry is coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals. The polarity of the frequency difference is defined in a tri-state having a positive state, a negative state, and a zero state.
Inventors
- 👤 Jan Filip
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:34
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/087; H03D; H03D13/00; H03D13/003; H03L7/095; H03L7/10; H03L7/113
Claims Analysis
Total Claims: 39
Claim 1
Independent Claim
209 words
A lock-in aid circuit for generating a signal for use in locking a second signal on a first signal, each of the first and second signals having an associated frequency, a first beat note signal and a second beat note signal being generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal, the circuit comprising: a first flip-flop configured to receive the first and second beat note signals for generating a first state signal, the first flip-flop generating the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal; a second flip-flop configured to receive the first and second beat note signals for generating a second state signal, the second flip-flop generating the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal; and detector circuitry coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals, the polarity of the frequency difference being defined in a tri-state having a positive state, a negative state, and a zero state.
Claim 2
Dependent Claim
209 words
A lock-in aid circuit for generating a signal for use in locking a second signal on a first signal, each of the first and second signals having an associated frequency, a first beat note signal and a second beat note signal being generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal, the circuit comprising: a first flip-flop configured to receive the first and second beat note signals for generating a first state signal, the first flip-flop generating the first state signal by sampling the second beat note signal at a first periodic interval of the first beat note signal; a second flip-flop configured to receive the first and second beat note signals for generating a second state signal, the second flip-flop generating the second state signal by sampling the second beat note signal at a second periodic interval of the first beat note signal; and detector circuitry coupled to receive the first and second state signals from the first and second flip-flops for detecting a polarity of the frequency difference between the first and second signals, the polarity of the frequency difference being defined in a tri-state having a positive state, a negative state, and a zero state.
Claim 3
Dependent Claim
102 words
The circuit as recited in claim 1, wherein the first flip-flop generates an inverse of the first state signal and wherein the detector circuitry further includes: an EXNOR gate coupled to receive the first and second state signals from the first and second flip-flops to generate a lock signal, the lock signal indicating whether the first signal is locked on the second signal; and a buffer coupled to receive the lock signal and the inverse of the first state signal for detecting the polarity of the frequency difference, the buffer generating a polarity signal indicating the detected polarity of the frequency difference.
Claim 4
Dependent Claim
21 words
The circuit as recited in claim 2, wherein the lock signal disables the buffer so as to output the zero state.
Claim 5
Dependent Claim
46 words
The circuit as recited in claim 1, wherein first flip-flop samples the second beat note signal at a rising edge of the first beat note signal and the second flip-flop samples the second beat note signal at a failing edge of the first beat note signal.
Claim 6
Dependent Claim
16 words
The circuit as recited in claim 1, wherein the first and second flip-flops are D flip-flops.
Claim 7
Dependent Claim
14 words
The circuit as recited in claim 2, wherein the buffer is a tri-state buffer.
Claim 8
Dependent Claim
24 words
The circuit as recited in claim 1, wherein the first signal is an input data signal and the second signal is a VCO signal.
Claim 9
Dependent Claim
21 words
The circuit as recited in claim 1, wherein the detected polarity is provided to a phase-locked loop to drive a VCO.
Claim 10
Dependent Claim
18 words
The circuit as recited in claim 7, wherein the input data signal is in an NRZ data format.
Claim 11
Dependent Claim
31 words
The circuit as recited in claim 1, wherein the first beat note signal is generated from the second signal and the second beat note is generated from a delayed second signal.
Claim 12
Dependent Claim
21 words
The circuit as recited in claim 10, wherein the delayed second signal is delayed between 45 and 135 degrees in phase.
Claim 13
Dependent Claim
51 words
The circuit as recited in claim 11, further comprising: a first phase detector configured to receive the first and second signals for generating the first beat note signal; and a second phase detector configured to receive the first signal and the delayed second signal for generating the second beat note signal.
Claim 14
Dependent Claim
24 words
The circuit as recited in claim 12, further comprising: a phase shifter configured to receive the second signal for generating the delayed second signal.
Claim 15
Independent Claim
175 words
A method for generating a lock-in aid signal, comprising: receiving a first signal and a second signal, each of the first and second signal having a frequency; developing a first beat note signal and a second beat note signal from the first and second signals when the frequencies of the first and second signals are not equal; sampling the second beat note at a first periodic interval of the first beat note signal to generate a first state signal; sampling the second beat note at a second periodic interval of the first beat note signal to generate a second state signal; determining a polarity signal indicating the polarity of the frequency difference between the first and second signals in response to an inverse state of the first state signal, the polarity of the frequency difference being defined as a tri-state having a positive state, a negative state, and a zero state; and generating a lock signal in response to the first and second state signals when the second signal is locked on the first signal.
Claim 16
Independent Claim
175 words
A method for generating a lock-in aid signal, comprising: receiving a first signal and a second signal, each of the first and second signal having a frequency; developing a first beat note signal and a second beat note signal from the first and second signals when the frequencies of the first and second signals are not equal; sampling the second beat note at a first periodic interval of the first beat note signal to generate a first state signal; sampling the second beat note at a second periodic interval of the first beat note signal to generate a second state signal; determining a polarity signal indicating the polarity of the frequency difference between the first and second signals in response to an inverse state of the first state signal, the polarity of the frequency difference being defined as a tri-state having a positive state, a negative state, and a zero state; and generating a lock signal in response to the first and second state signals when the second signal is locked on the first signal.
Claim 17
Dependent Claim
28 words
The method as recited in claim 14, further comprising: when the lock signal is generated, disabling the polarity signal so as to generate the polarity of zero state.
Claim 18
Dependent Claim
39 words
The method as recited in claim 14, wherein the first periodic interval corresponds to every rising edge of the first beat note signal and the second periodic interval corresponds to every falling edge of the first beat note signal.
Claim 19
Dependent Claim
24 words
The method as recited in claim 14, wherein the first signal is an input data signal and the second signal is a VCO signal.
Claim 20
Dependent Claim
60 words
The method as recited in claim 17, wherein the input data signal is an NRZ data signal and the VCO signal is from a phase-locked loop, wherein the method further comprises: providing the polarity of the frequency difference to the phase-locked loop to bring the second signal toward lock with the first signal when the polarity signal is not disabled.
Claim 21
Dependent Claim
20 words
The method as recited in claim 18, wherein the first and second beat notes are generated by a phase detector.
Claim 22
Dependent Claim
23 words
The method as recited in claim 18, wherein the first and second state signals are generated by a first and second flip-flops, respectively.
Claim 23
Dependent Claim
30 words
The method as recited in claim 14, wherein the polarity is the inverse state of the first state signal when the second signal is not locked on the first signal.
Claim 24
Dependent Claim
16 words
The method as recited in claim 15, wherein the polarity signal is generated by a buffer.
Claim 25
Dependent Claim
25 words
The method as recited in claim 22, wherein the generated lock signal disables the buffer when the second signal is locked on the first signal.
Claim 26
Dependent Claim
31 words
The method as recited in claim 14, wherein the first beat note signal is generated from the second signal and the second beat note is generated from a delayed second signal.
Claim 27
Dependent Claim
21 words
The method as recited in claim 24, wherein the delayed second signal is delayed between 90 and 135 degrees in phase.
Claim 28
Dependent Claim
189 words
A lock-in aid circuit for generating a signal for use in locking a second signal on a first signal, each of the first and second signals having an associated frequency, a first beat note signal and a second beat note signal being generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal, the circuit comprising: first state generating means for generating a first state signal in response to the first and second beat note signals by sampling the second beat note signal at a first periodic interval of the first beat note signal; second state generating means for generating a second state signal in response to the first and second beat note signals by sampling the second beat note signal at a second periodic interval of the first beat note signal; and detecting means for detecting a polarity of the frequency difference between the first and second signals in response to the first and second state signals, the polarity of the frequency difference being defined in a tri-state having a positive state, a negative state, and a zero state.
Claim 29
Dependent Claim
189 words
A lock-in aid circuit for generating a signal for use in locking a second signal on a first signal, each of the first and second signals having an associated frequency, a first beat note signal and a second beat note signal being generated from the first and second signals, respectively, when the frequencies of the first and second signals are not equal, the circuit comprising: first state generating means for generating a first state signal in response to the first and second beat note signals by sampling the second beat note signal at a first periodic interval of the first beat note signal; second state generating means for generating a second state signal in response to the first and second beat note signals by sampling the second beat note signal at a second periodic interval of the first beat note signal; and detecting means for detecting a polarity of the frequency difference between the first and second signals in response to the first and second state signals, the polarity of the frequency difference being defined in a tri-state having a positive state, a negative state, and a zero state.
Claim 30
Dependent Claim
78 words
The circuit as recited in claim 26, wherein the detector circuitry further includes: lock signal generating means for generating a lock signal in response to the first and second state signals, the lock signal indicating whether the first signal is locked on the second signal; and buffer means for outputting a polarity in response to the lock signal and to an inverse of the first state signal, the polarity signal indicating the detected polarity of the frequency difference.
Claim 31
Dependent Claim
22 words
The circuit as recited in claim 27, wherein the lock signal disables the buffer means so as to output the zero state.
Claim 32
Dependent Claim
50 words
The circuit as recited in claim 26, wherein first state generating means samples the second beat note signal at a rising edge of the first beat note signal and the second state generating means samples the second beat note signal at a falling edge of the first beat note signal.
Claim 33
Dependent Claim
24 words
The circuit as recited in claim 26, wherein the first signal is an input data signal and the second signal is a VCO signal.
Claim 34
Dependent Claim
21 words
The circuit as recited in claim 26, wherein the detected polarity is provided to a phase-locked loop to drive a VCO.
Claim 35
Dependent Claim
18 words
The circuit as recited in claim 30, wherein the input data signal is in an NRZ data formnat.
Claim 36
Dependent Claim
31 words
The circuit as recited in claim 26, wherein the first beat note signal is generated from the second signal and the second beat note is generated from a delayed second signal.
Claim 37
Dependent Claim
21 words
The circuit as recited in claim 33, wherein the delayed second signal is delayed between 45 and 135 degrees in phase.
Claim 38
Dependent Claim
51 words
The circuit as recited in claim 26, further comprising: a first phase detector configured to receive the first and second signals for generating the first beat note signal; and a second phase detector configured to receive the first signal and the delayed second signal for generating the second beat note signal.
Claim 39
Dependent Claim
24 words
The circuit as recited in claim 35, further comprising: a phase shifter configured to receive the second signal for generating the delayed second signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-27 | 2003-12-27 | 2004-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-27 | 2007-12-27 | 2008-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-27 | 2011-12-27 | 2012-06-27 | $7700.00 | Window Closed / Lapsed |