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US6078088A
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Low dielectric semiconductor device with rigid lined interconnection system
Assignee: GlobalFoundries Inc
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Filing: 1999-01-05
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Granted: 2000-06-20
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Expires: 2019-01-05
Abstract
Abstract Multi-level semiconductor devices are formed with reduced parasitic capacitance without sacrificing structural integrity or electromigation performance by removing the inter-layer dielectrics and supporting the interconnection system with a rigid lining. Embodiments include depositing a dielectric sealing layer, e.g., silicon oxide, silicon nitride or composite of silicon oxide/silicon nitride, before forming the first metallization level, removing the inter-layer dielectrics after forming the last metallization level, lining the interconnection system with undoped polycrystalline silicon and forming a dielectric protective layer, e.g. a silane derived oxide, on the uppermost metallization level.
Inventors
- 👤 Matthew S. Buynoski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 04:39
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/495; H10W20/45; H10W20/48
Claims Analysis
Total Claims: 25
Claim 1
Independent Claim
114 words
A semiconductor device comprising: a substrate having active regions; and an interconnection system comprising: a first patterned metal layer, comprising metal features, over the substrate; a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer; vias electrically connecting metal features of different patterned metal layers; contacts electrically connecting active regions to metal features of the first patterned metal layer; air gaps substantially continuous between the patterned metal layers, metal features, and vias; and a liner, comprising a material different from the metal features, on the metal features and vias, wherein the interconnection is continuously enveloped by the liner.
Claim 2
Dependent Claim
114 words
A semiconductor device comprising: a substrate having active regions; and an interconnection system comprising: a first patterned metal layer, comprising metal features, over the substrate; a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer; vias electrically connecting metal features of different patterned metal layers; contacts electrically connecting active regions to metal features of the first patterned metal layer; air gaps substantially continuous between the patterned metal layers, metal features, and vias; and a liner, comprising a material different from the metal features, on the metal features and vias, wherein the interconnection is continuously enveloped by the liner.
Claim 3
Dependent Claim
21 words
The semiconductor device according to claim 1, further comprising a dielectric sealing layer between the substrate and first patterned metal layer.
Claim 4
Dependent Claim
19 words
The semiconductor device according to claim 2, further comprising a dielectric protective layer on the uppermost patterned metal layer.
Claim 5
Dependent Claim
112 words
A semiconductor device comprising: a substrate having active regions; and an interconnection system comprising: a first patterned metal layer, comprising metal features, over the substrate; a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer; vias electrically connecting metal features of different patterned metal layers; contacts electrically connecting active regions to metal features of the first patterned metal layer; air gaps substantially continuous between the patterned metal layers, metal features, and vias; and a liner, comprising a material different from the metal features, on the metal features and vias, wherein the liner comprises undoped polycrystalline silicon.
Claim 6
Dependent Claim
112 words
A semiconductor device comprising: a substrate having active regions; and an interconnection system comprising: a first patterned metal layer, comprising metal features, over the substrate; a plurality of patterned metal layers, each patterned metal layer containing metal features, above the first patterned metal layer terminating with an uppermost patterned metal layer; vias electrically connecting metal features of different patterned metal layers; contacts electrically connecting active regions to metal features of the first patterned metal layer; air gaps substantially continuous between the patterned metal layers, metal features, and vias; and a liner, comprising a material different from the metal features, on the metal features and vias, wherein the liner comprises undoped polycrystalline silicon.
Claim 7
Dependent Claim
24 words
The semiconductor device according to claim 4, wherein the undoped polycrystalline silicon liner has a thickness of about 500 Å to about 1,000 Å.
Claim 8
Dependent Claim
26 words
The semiconductor device according to claim 4, wherein the dielectric sealing layer comprises a silicon oxide, silicon nitride, or composite of silicon nitride on silicon oxide.
Claim 9
Dependent Claim
22 words
The semiconductor device according to claim 6, wherein the sealing layer has a thickness of about 500 Å to about 1,000 Å.
Claim 10
Dependent Claim
15 words
The semiconductor device according to claim 6, wherein the dielectric protective layer comprises an oxide.
Claim 11
Dependent Claim
14 words
The semiconductor device according to claim 8, wherein the oxide is derived from silane.
Claim 12
Dependent Claim
24 words
The semiconductor device according to claim 8, wherein the dielectric protective oxide layer has a thickness of about 10,000 Å to about 25,000 Å.
Claim 13
Dependent Claim
21 words
The semiconductor device according to claim 4, further comprising a dielectric sealing layer between the substrate and first patterned metal layer.
Claim 14
Dependent Claim
19 words
The semiconductor device according to claim 11, further comprising a dielectric protective layer on the uppermost patterned metal layer.
Claim 15
Dependent Claim
17 words
The semiconductor device according to claim 4, wherein the interconnection system is continuously enveloped by the liner.
Claim 16
Independent Claim
104 words
A method of manufacturing a semiconductor device, the method comprising: forming a substrate with active regions; forming an interconnection system comprising: a first patterned metal layer, over the substrate, having metal features electrically connected to the active regions by contacts; a plurality of patterned metal layers over the first patterned metal layer terminating with an upper most patterned metal layer, each patterned metal layer having metal features electrically connected to metal features of different patterned metal layers by vias; and an inter-layer dielectric between patterned metal layers; removing the inter-layer dielectrics; and forming a liner, comprising undoped polycrystalline silicon, on the features and vias.
Claim 17
Independent Claim
104 words
A method of manufacturing a semiconductor device, the method comprising: forming a substrate with active regions; forming an interconnection system comprising: a first patterned metal layer, over the substrate, having metal features electrically connected to the active regions by contacts; a plurality of patterned metal layers over the first patterned metal layer terminating with an upper most patterned metal layer, each patterned metal layer having metal features electrically connected to metal features of different patterned metal layers by vias; and an inter-layer dielectric between patterned metal layers; removing the inter-layer dielectrics; and forming a liner, comprising undoped polycrystalline silicon, on the features and vias.
Claim 18
Dependent Claim
28 words
The method according to claim 14, further comprising: forming a dielectric sealing layer on the substrate; and forming the first patterned metal layer on the dielectric sealing layer.
Claim 19
Dependent Claim
19 words
The method according to claim 15, further comprising forming a dielectric protective layer on the uppermost patterned metal layer.
Claim 20
Dependent Claim
34 words
The method according to claim 16, comprising forming the inter-layer dielectrics by depositing layers of a: lead-rich glass soluble in acetic acid; benzocyclobutene resin; or silica at a temperature less than about 400° C.
Claim 21
Dependent Claim
26 words
The method according to claim 17, comprising: forming the inter-layer dielectrics by depositing layers of a lead-rich glass; and removing the inter-layer dielectrics with acetic acid.
Claim 22
Dependent Claim
29 words
The method according to claim 17, comprising: forming the inter-layer dielectrics by depositing layers of benzocyclobutene resin; and removing the inter-layer dielectrics with a mixed oxygen and fluorine plasma.
Claim 23
Dependent Claim
39 words
The method according to claim 17, comprising: forming the inter-layer dielectrics by depositing layers of silica at a temperature less than about 400° C.; and removing the inter-layer dielectrics with a neutral or slightly acidic buffered hydrofluoric acid solution.
Claim 24
Dependent Claim
25 words
The method according to claim 14, wherein the dielectric sealing layer comprises a silicon oxide, silicon nitride, or composite of silicon nitride on silicon oxide.
Claim 25
Dependent Claim
14 words
The method according to claim 21, wherein the dielectric protective layer comprises an oxide.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-20 | 2003-12-20 | 2004-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-20 | 2007-12-20 | 2008-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-20 | 2011-12-20 | 2012-06-20 | $7700.00 | Window Closed / Lapsed |