Patent US6075730A successfully refreshed from Google Patents.
US6075730A
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High performance cost optimized memory with delayed memory writes
Assignee: Rambus Inc
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Filing: 1998-10-09
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Granted: 2000-06-13
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Expires: 2018-10-09
Abstract
Abstract A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core write transaction such that the memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction. The delay circuit delays the memory core write transaction for a time corresponding to the time required for signals to travel on the interconnect.
Inventors
- 👤 Richard M. Barth
- 👤 Frederick A. Ware
- 👤 Donald C. Stark
- 👤 Craig E. Hampel
- 👤 Paul G. Davis
- 👤 Abhijit M. Abhyankar
- 👤 James A. Gasbarro
- 👤 David Nguyen
- 👤 Thomas J. Holman
- 👤 Andrew V. Anderson
- 👤 Peter D. MacWilliams
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 11:55
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/22; G11C7/10; G11C7/1072; G11C2207/00; G11C2207/22; G11C2207/229
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
143 words
A memory device, comprising: a plurality of connections for coupling to an interconnect structure for receiving row operation information, column operation information, and data information, said column operation information including read commands and write commands, said data information including read data and write data; a memory core for storing said data information; and memory interface circuitry coupled to said plurality of connections and said memory core, for generating row timing signals and column timing signals to operate on said memory core in response to said row operation information and said column operation information, said memory interface circuitry including circuitry for delaying a write operation at said memory core by delaying said column timing signals such that the delay at said plurality of connections between a write command and write data is approximately equal to the delay between a read command and read data.
Claim 2
Dependent Claim
143 words
A memory device, comprising: a plurality of connections for coupling to an interconnect structure for receiving row operation information, column operation information, and data information, said column operation information including read commands and write commands, said data information including read data and write data; a memory core for storing said data information; and memory interface circuitry coupled to said plurality of connections and said memory core, for generating row timing signals and column timing signals to operate on said memory core in response to said row operation information and said column operation information, said memory interface circuitry including circuitry for delaying a write operation at said memory core by delaying said column timing signals such that the delay at said plurality of connections between a write command and write data is approximately equal to the delay between a read command and read data.
Claim 3
Dependent Claim
32 words
The memory device of claim 1 wherein said memory interface circuitry includes circuitry to delay said column timing signals for a time period within the duration of a t RAS ,MIN signal.
Claim 4
Dependent Claim
36 words
The memory device of claim 1 wherein said memory interface circuitry includes circuitry to delay said column timing signals for a time corresponding to the time required for signals to travel on said plurality of connections.
Claim 5
Dependent Claim
73 words
A memory device, comprising: an interconnect including control terminals and bidirectional data terminals ; a memory core for storing data; and a memory interface circuit connected to said interconnect and said memory core, said memory interface circuit including a delay circuit to establish a write delay during a memory core write transaction such that said memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction.
Claim 6
Dependent Claim
73 words
A memory device, comprising: an interconnect including control terminals and bidirectional data terminals ; a memory core for storing data; and a memory interface circuit connected to said interconnect and said memory core, said memory interface circuit including a delay circuit to establish a write delay during a memory core write transaction such that said memory core write transaction has a processing time that is substantially equivalent to a memory core read transaction.
Claim 7
Dependent Claim
35 words
The memory device of claim 4 wherein said memory interface circuit includes a delay circuit to delay said memory core write transaction for a time period within the duration of a t RAS ,MIN signal.
Claim 8
Dependent Claim
37 words
The memory device of claim 4 wherein said memory interface circuitry includes a delay circuit to delay said memory core write transaction for a time corresponding to the time required for signals to travel on said interconnect.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-13 | 2003-12-13 | 2004-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-13 | 2007-12-13 | 2008-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-13 | 2011-12-13 | 2012-06-13 | $7700.00 | Window Closed / Lapsed |