Patent US6074956A successfully refreshed from Google Patents.
US6074956A
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Method for preventing silicide residue formation in a semiconductor device
Assignee: Monterey Research LLC
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Filing: 1998-05-12
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Granted: 2000-06-13
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Expires: 2018-05-12
Abstract
Abstract An etching process is provided for etching through a tungsten silicide layer and an underlying polysilicon layer during the formation of a control gate in a semiconductor device. The etching process prevents the formation of a tungsten silicide residue while etching a layer of tungsten silicide, by employing a plasma that exhibits strong physical sputtering capabilities. The plasma effectively etches away exposed portions of the silicide layer, especially in narrow patterned regions. The plasma exhibits an etching selectivity (ratio of tungsten silicide etch rate to polysilicon etch rate) that is less than about 1.0.
Inventors
- 👤 Wenge Yang
- 👤 Lewis Shen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:16
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/30; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; H10P50/266; H10P50/267; H10P50/268
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
119 words
A method for fabricating a semiconductor device, the method comprising: forming a gate structure on a substrate; forming at least one dielectric material on the gate structure; forming a layer stack on the dielectric material, the layer stack comprising a polysilicon gate material that is formed on the dielectric material and a tungsten silicide that is formed on the polysilicon gate material; and adjusting an amount of electrical energy output by source and bias power supplies to substantially prevent silicide formation during a selective removal of a portion of the layer stack using a plasma having an etching rate selectivity of tungsten silicide to polysilicon of less than about 1.0, to expose a portion of the underlying dielectric material.
Claim 2
Independent Claim
119 words
A method for fabricating a semiconductor device, the method comprising: forming a gate structure on a substrate; forming at least one dielectric material on the gate structure; forming a layer stack on the dielectric material, the layer stack comprising a polysilicon gate material that is formed on the dielectric material and a tungsten silicide that is formed on the polysilicon gate material; and adjusting an amount of electrical energy output by source and bias power supplies to substantially prevent silicide formation during a selective removal of a portion of the layer stack using a plasma having an etching rate selectivity of tungsten silicide to polysilicon of less than about 1.0, to expose a portion of the underlying dielectric material.
Claim 3
Dependent Claim
23 words
The method as recited in claim 1, wherein the plasma exhibits an etching rate selectivity of tungsten silicide to polysilicon of about 0.8.
Claim 4
Dependent Claim
93 words
The method as recited in claim 1, wherein said selective removal is performed in an etching tool having a source power supply and a bias power supply, and the step of selectively removing includes supplying between about 300 and about 2000 Watts of electrical energy from the source power supply to the etching tool and between about 120 and about 200 Watts of electrical energy from the bias power supply to the etching tool to generate the plasma from an etchant chemistry comprising a mixture of Cl 2 /N 2 /He-O 2 gasses.
Claim 5
Dependent Claim
44 words
The method as recited in claim 3, wherein the etchant chemistry comprises between about 80 and about 90 percent Cl 2 gas, between about 1 and about 10 percent N 2 gas, and between about 1 and about 10 percent He-O 2 gas mixture.
Claim 6
Dependent Claim
41 words
The method as recited in claim 1, wherein the layer stack further includes at least one layer of materials over the silicide, the layer of materials selected from a set of materials including polysilicon, silicon dioxide, silicon nitride, and silicon oxynitride.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-13 | 2003-12-13 | 2004-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-13 | 2007-12-13 | 2008-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-13 | 2011-12-13 | 2012-06-13 | $7700.00 | Window Closed / Lapsed |