US6074937A
Expired / Lapsed
US
⏱️ 0.0 years remaining
End-of-range damage suppression for ultra-shallow junction formation
Assignee: GlobalFoundries Inc
•
Filing: 1998-04-13
•
Granted: 2000-06-13
•
Expires: 2018-04-13
Abstract
Abstract Lightly doped regions are implanted into an amorphous region in the semiconductor substrate to significantly reduce transient enhanced diffusion upon subsequent activation annealing. A sub-surface non-amorphous region is also formed before activation annealing to substantially eliminate end-of-range defects on crystallization of amorphous region containing the lightly doped implants.
Inventors
- 👤 Shekhar Pramanick
- 👤 Che-Hoo Ng
- 👤 Emi Ishida
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 20:54
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10P; H10P30/00; H10P30/20; H10P30/202; H10P30/204; H10P30/208; H10P30/21; H10P30/212
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
116 words
A method of manufacturing a semiconductor device, which method comprises: ion implanting impurities to form a sub-surface non-amorphous region extending below, but not extending from, a surface of a semiconductor substrate to a first depth and generate a vacancy-rich region between the sub-surface non-amorphous region and the surface of the semiconductor substrate; ion implanting impurities to form a surface amorphous region extending from and below the surface of the semiconductor substrate to a second depth and generate an interstitial region substantially overlapping the vacancy-rich region; providing dopant impurities within the surface amorphous region; and activation annealing the dopant impurities to form lightly doped source/drain regions extending below the surface of semiconductor substrate to a third depth.
Claim 2
Independent Claim
116 words
A method of manufacturing a semiconductor device, which method comprises: ion implanting impurities to form a sub-surface non-amorphous region extending below, but not extending from, a surface of a semiconductor substrate to a first depth and generate a vacancy-rich region between the sub-surface non-amorphous region and the surface of the semiconductor substrate; ion implanting impurities to form a surface amorphous region extending from and below the surface of the semiconductor substrate to a second depth and generate an interstitial region substantially overlapping the vacancy-rich region; providing dopant impurities within the surface amorphous region; and activation annealing the dopant impurities to form lightly doped source/drain regions extending below the surface of semiconductor substrate to a third depth.
Claim 3
Dependent Claim
12 words
The method according to claim 1, wherein the semiconductor substrate comprises silicon.
Claim 4
Dependent Claim
19 words
The method according to claim 2, wherein the sub-surface non-amorphous and surface amorphous regions are crystallized during activation annealing.
Claim 5
Dependent Claim
14 words
The method according to claim 2, wherein the first depth exceeds the second depth.
Claim 6
Dependent Claim
20 words
The method according to claim 4, wherein the first depth exceeds the second depth by up to about 200 Å.
Claim 7
Dependent Claim
30 words
The method according to claim 5, wherein the first depth is about 700 Å to about 900 Å, and the second depth is about 500 Å to about 800 Å.
Claim 8
Dependent Claim
16 words
The method according to claim 6, wherein the third depth is less than about 800 Å.
Claim 9
Dependent Claim
37 words
The method according to claim 7, wherein the first depth is about 800 Å, the second depth is about 600 Å to about 700 Å, and the third depth is about 500 Å to about 600 Å.
Claim 10
Dependent Claim
31 words
The method according to claim 2, comprising ion implanting impurities to form the sub-surface non-amorphous and amorphous silicon regions, and ion implanting dopant impurities which form the lightly doped source/drain regions.
Claim 11
Dependent Claim
24 words
The method according to claim 1, comprising: implanting silicon or germanium ions to form the sub-surface non-amorphous silicon region and the amorphous silicon region.
Claim 12
Dependent Claim
34 words
The method according to claim 10, comprising: implanting boron ions into the amorphous region activation annealing at a temperature of about 500° C. to about 900° C. to form the lightly doped source/drain regions.
Claim 13
Dependent Claim
118 words
The method according to claim 3, comprising sequentially: forming a dielectric layer on the surface of the silicon semiconductor substrate; forming a polycrystalline silicon layer on the dielectric layer; patterning the polycrystalline silicon layer to form a gate electrode on the dielectric layer; ion implanting impurities through the dielectric layer, using the gate electrode as a mask, to form the sub-surface non-amorphous and surface amorphous regions; patterning the dielectric layer to form a gate dielectric layer under the polycrystalline silicon gate electrode, thereby exposing the surface of the semiconductor substrate; ion implanting boron, using the gate electrode as a mask; and activation annealing to diffuse and activate the implanted boron ions to form the lightly doped source/drain regions.
Claim 14
Dependent Claim
87 words
The method according to claim 12, comprising sequentially: forming sidewall insulating spacers on side surfaces of the gate electrode after forming the sub-surface non-amorphous and amorphous silicon regions; ion implanting impurities and activation annealing to form moderate or highly doped source/drain regions; forming the sub-surface non-amorphous and surface amorphous regions; patterning the dielectric layer to form a gate dielectric layer under the gate electrode exposing the surface of the semiconductor substrate; and ion implanting boron into the surface amorphous region to form the lightly doped source/drain regions.
Claim 15
Dependent Claim
20 words
The method according to claim 2, comprising forming the sub-surface non-amorphous silicon region before forming the surface amorphous silicon region.
Claim 16
Dependent Claim
20 words
The method according to claim 2, comprising forming the surface amorphous silicon region before forming the sub-surface non-amorphous silicon region.
Claim 17
Dependent Claim
16 words
The method according to claim 1, wherein interstitials in the interstitial rich region are substantially annihilated.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-13 | 2003-12-13 | 2004-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-13 | 2007-12-13 | 2008-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-13 | 2011-12-13 | 2012-06-13 | $7700.00 | Window Closed / Lapsed |