Patent US6074909A successfully refreshed from Google Patents.
US6074909A
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Apparatus and method for forming controlled deep trench top isolation layers
Assignee: Polaris Innovations Ltd
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Filing: 1998-07-31
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Granted: 2000-06-13
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Expires: 2018-07-31
Abstract
Abstract A method for controlling isolation layer thickness in deep trenches for semiconductor memories in accordance with the present invention includes the steps of providing a deep trench having a storage node formed therein, the storage node having a buried strap, depositing an isolation layer on the buried strap for providing electrical isolation for the storage node, forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap and removing the isolation layer except the portion masked by the mask layer such that control of a thickness of the isolation layer is improved. A method for fabricating vertical transistors by recessing a substrate to permit increased overlap between a transistor channel and buried strap outdiffusion when the transistor is formed is also included. A semiconductor device is also disclosed.
Inventors
- 👤 Ulrike Gruening
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:45
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10P; H10P14/00; H10P14/40; H10B12/05; H10B12/053; H10B12/30; H10B12/48; H10B12/488
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
85 words
A method for controlling isolation layer thickness in trenches for semiconductor memories comprising the steps of: providing a deep trench having a storage node formed therein, the storage node having a buried strap; depositing an isolation layer on the buried strap for providing electrical isolation for the storage node; forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap; and removing the isolation layer other than the portion masked by the mask layer.
Claim 2
Independent Claim
85 words
A method for controlling isolation layer thickness in trenches for semiconductor memories comprising the steps of: providing a deep trench having a storage node formed therein, the storage node having a buried strap; depositing an isolation layer on the buried strap for providing electrical isolation for the storage node; forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap; and removing the isolation layer other than the portion masked by the mask layer.
Claim 3
Dependent Claim
24 words
The method as recited in claim 1, wherein the step of depositing the isolation layer includes depositing the isolation layer by chemical vapor deposition.
Claim 4
Dependent Claim
26 words
The method as recited in claim 1, wherein the step of depositing the isolation layer includes depositing the isolation layer by plasma enhanced chemical vapor deposition.
Claim 5
Dependent Claim
14 words
The method as recited in claim 1, wherein the isolation layer includes an oxide.
Claim 6
Dependent Claim
14 words
The method as recited in claim 1, wherein the isolation layer includes a nitride.
Claim 7
Dependent Claim
23 words
The method as recited in claim 1, wherein the thickness of the isolation layer is between about 20 nm to about 50 nm.
Claim 8
Dependent Claim
31 words
The method as recited in claim 1, wherein the step of forming the masking layer includes the step of depositing a material which is selectively etchable relative to the isolation layer.
Claim 9
Dependent Claim
12 words
The method as recited in claim 7, wherein the material includes polysilicon.
Claim 10
Independent Claim
125 words
A method for fabricating a memory cell having trench isolation comprising the steps of: providing a deep trench having a storage node formed therein, the storage node having a buried strap; depositing an isolation layer on the buried strap for providing electrical isolation for the storage node; forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap; selectively etching the isolation layer relative to the masking layer to leave the portion masked by the masking layer; opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench; filling the isolation trench with a dielectric material to provide trench isolation.
Claim 11
Independent Claim
125 words
A method for fabricating a memory cell having trench isolation comprising the steps of: providing a deep trench having a storage node formed therein, the storage node having a buried strap; depositing an isolation layer on the buried strap for providing electrical isolation for the storage node; forming a masking layer on the isolation layer to mask a portion of the isolation layer in contact with the buried strap; selectively etching the isolation layer relative to the masking layer to leave the portion masked by the masking layer; opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench; filling the isolation trench with a dielectric material to provide trench isolation.
Claim 12
Dependent Claim
30 words
The method as recited in claim 9, further comprises the step of forming an access device for accessing the storage node disposed within the deep trench below the isolation layer.
Claim 13
Dependent Claim
35 words
The method as recited in claim 10, wherein the step of forming an access device includes forming a transistor having a channel formed in the substrate for electrically coupling the buried strap to a bitline.
Claim 14
Dependent Claim
36 words
The method as recited in claim 11, further comprises the step of recessing the portion of the substrate adjacent to the deep trench such that the transistor is formed a greater distance away from the trench.
Claim 15
Dependent Claim
35 words
The method as recited in claim 9, further comprises the step of forming a transistor gate adjacent to the trench isolation and adjacent to the isolation layer in a top portion of the deep trench.
Claim 16
Dependent Claim
24 words
The method as recited in claim 9, wherein the step of depositing the isolation layer includes depositing the isolation layer by chemical vapor deposition.
Claim 17
Dependent Claim
14 words
The method as recited in claim 9, wherein the isolation layer includes an oxide.
Claim 18
Dependent Claim
14 words
The method as recited in claim 9, wherein the isolation layer includes a nitride.
Claim 19
Dependent Claim
23 words
The method as recited in claim 9, wherein the thickness of the isolation layer is between about 20 nm to about 50 nm.
Claim 20
Dependent Claim
13 words
The method as recited in claim 9, wherein the masking layer includes polysilicon.
Claim 21
Dependent Claim
15 words
The method as recited in claim 9, wherein the trench isolation includes shallow trench isolation.
Claim 22
Dependent Claim
16 words
The method as recited in claim 9, wherein the trench isolation includes raised shallow trench isolation.
Claim 23
Independent Claim
107 words
A method for fabricating a vertical transistor comprising the steps of: providing a substrate having trenches formed therein, each trench having a storage node formed therein, the storage node having a buried strap; forming an isolation layer on the buried strap; laterally etching the substrate to form a recess into the substrate such that the recess extends beyond sides of the trench, the recess being in communication with the trench; and forming a gate conductor in the recess such that a channel is formed adjacent to the gate conductor for providing electrical conduction between the buried strap and a conductive line upon activation of the gate conductor.
Claim 24
Independent Claim
107 words
A method for fabricating a vertical transistor comprising the steps of: providing a substrate having trenches formed therein, each trench having a storage node formed therein, the storage node having a buried strap; forming an isolation layer on the buried strap; laterally etching the substrate to form a recess into the substrate such that the recess extends beyond sides of the trench, the recess being in communication with the trench; and forming a gate conductor in the recess such that a channel is formed adjacent to the gate conductor for providing electrical conduction between the buried strap and a conductive line upon activation of the gate conductor.
Claim 25
Dependent Claim
21 words
The method as recited in claim 21, wherein the step of laterally etching includes laterally etching by a dry etch process.
Claim 26
Dependent Claim
29 words
The method as recited in claim 21, wherein the step of laterally etching includes laterally etching by one of a chemical downstream etch and a reactive ion etch process.
Claim 27
Dependent Claim
14 words
The method as recited in claim 21, wherein the conductive line includes a bitline.
Claim 28
Independent Claim
143 words
A method for fabricating a vertical transistor for semiconductor memories with deep trenches comprising the steps of: providing a substrate having deep trenches formed therein, each deep trench having a storage node formed therein, the storage node having a buried strap recessed below a top surface of the substrate; forming an isolation layer on the buried strap and on trench sidewalls; depositing a dummy layer on the isolation layer; opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench; filling the isolation trench with a dielectric material to provide trench isolation; selectively etching the dummy layer relative to the dielectric material and the isolation layer; removing the isolation layer from the trench sidewalls; and forming a vertical transistor adjacent to the portion of the substrate that was removed.
Claim 29
Independent Claim
143 words
A method for fabricating a vertical transistor for semiconductor memories with deep trenches comprising the steps of: providing a substrate having deep trenches formed therein, each deep trench having a storage node formed therein, the storage node having a buried strap recessed below a top surface of the substrate; forming an isolation layer on the buried strap and on trench sidewalls; depositing a dummy layer on the isolation layer; opening up an isolation trench in communication with the deep trench by removing at least a portion of the substrate adjacent to the deep trench; filling the isolation trench with a dielectric material to provide trench isolation; selectively etching the dummy layer relative to the dielectric material and the isolation layer; removing the isolation layer from the trench sidewalls; and forming a vertical transistor adjacent to the portion of the substrate that was removed.
References Cited (Backward Citations)
US5482883A
Cited
US5831301A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-06-13 | 2003-12-13 | 2004-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-06-13 | 2007-12-13 | 2008-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-06-13 | 2011-12-13 | 2012-06-13 | $7700.00 | Window Closed / Lapsed |