Programmable sense amplifier delay (PSAD) circuit which is matched to the memory array

Claim 2

An inverter which responds to a predetermined voltage drop, the inverter comprising: a two transistor inverter controlled by a varying control signal and receiving a voltage source signal as input; and means for producing and applying a reference current through said two transistor inverter, wherein said reference current is fixed with respect to the voltage level of said voltage source, wherein said two transistor inverter trips when said varying control signal is below said voltage source signal by a predetermined amount that is fixed with respect to temperature and to the voltage level of said voltage source.

Claim 3

An inverter according to claim 1 wherein said means for producing and applying includes: at least one transistor controlled by a reference signal and receiving a voltage source as input, wherein said reference signal tracks said voltage source, the at least one transistor producing a second reference current; and a current mirror connected between the output of said at least one transistor and a ground connection of said two transistor inverter for mirroring a version of said second reference current to said ground connection, thereby to produce said first reference current.

Claim 4

An inverter according to claim 1 and wherein said predetermined amount is defined by the size of said two transistor inverter and the strength of said first reference current.

Claim 5

An inverter according to claim 1 wherein said first reference current varies with temperature, wherein said two transistor inverter comprises one p-channel transistor and one n-channel transistor, wherein said p-channel transistor is biased to match the temperature variation of said first reference current.

Claim 6

A programmable sense amplifier delay (PSAD) circuit which is matched to the response time of a memory array, the memory array having a multiplicity of memory cells, the PSAD circuit comprising: an inverter having an input line and receiving a voltage source Vcc, said inverter responding to the predetermined voltage drop between the voltage level of said voltage source Vcc and the voltage on said input line, wherein said inverter is insensitive to changes in temperature and the voltage level of a voltage source; a pre-charging, p-channel, pull-up transistor, connected between said voltage source Vcc and said input line and activatable during a pre-charge phase of said memory array to raise the voltage level of said input line towards said voltage source; a pull-down transistor of the type of said memory cells connected between said input line and a ground source and activatable after said pre-charge phase to discharge the voltage level of said input line; and a plurality of capacitors selectively connected in parallel to said pull-down transistor, said capacitors defining the speed at which said pull-down transistor discharges said input line.

Claim 7

A programmable sense amplifier delay (PSAD) circuit which is matched to the response time of a memory array, the memory array having a multiplicity of memory cells, the PSAD circuit comprising: an inverter having an input line and receiving a voltage source Vcc, said inverter responding to the predetermined voltage drop between the voltage level of said voltage source Vcc and the voltage on said input line, wherein said inverter is insensitive to changes in temperature and the voltage level of a voltage source; a pre-charging, p-channel, pull-up transistor, connected between said voltage source Vcc and said input line and activatable during a pre-charge phase of said memory array to raise the voltage level of said input line towards said voltage source; a pull-down transistor of the type of said memory cells connected between said input line and a ground source and activatable after said pre-charge phase to discharge the voltage level of said input line; and a plurality of capacitors selectively connected in parallel to said pull-down transistor, said capacitors defining the speed at which said pull-down transistor discharges said input line.

Claim 8

A programmable sense amplifier delay (PSAD) circuit which is matched to the response time of a memory array, the memory array having a multiplicity of memory cells, the PSAD circuit comprising: an inverter having an input line and receiving a voltage source Vcc, said inverter responding to a predetermined voltage drop between the voltage level of said voltage source Vcc and the voltage on said input line wherein said inverter includes: a two transistor inverter controlled by a varying control signal and receiving said voltage source Vcc as input; and means for producing and applying a reference current through said two transistor inverter, wherein said reference current is fixed with respect to the voltage level of said voltage source Vcc, wherein said two transistor inverter trips when said varying control signal is below the voltage level of said voltage source Vcc by a predetermined amount that is fixed with respect to temperature and to the voltage level of said voltage source Vcc; a pre-charging, p-channel, pull-up transistor, connected between said voltage source Vcc and said input line and activatable during a pre-charge phase of said memory array to raise the voltage level of said input line towards said voltage source; a pull-down transistor of the type of said memory cells connected between said input line and a ground source and activatable after said pre-charge phase to discharge the voltage level of said input line; and a plurality of capacitors selectively connected in parallel to said pull-down transistor, said capacitors defining the speed at which said pull-down transistor discharges said input line.

Claim 9

A programmable sense amplifier delay (PSAD) circuit which is matched to the response time of a memory array, the memory array having a multiplicity of memory cells, the PSAD circuit comprising: an inverter having an input line and receiving a voltage source Vcc, said inverter responding to a predetermined voltage drop between the voltage level of said voltage source Vcc and the voltage on said input line wherein said inverter includes: a two transistor inverter controlled by a varying control signal and receiving said voltage source Vcc as input; and means for producing and applying a reference current through said two transistor inverter, wherein said reference current is fixed with respect to the voltage level of said voltage source Vcc, wherein said two transistor inverter trips when said varying control signal is below the voltage level of said voltage source Vcc by a predetermined amount that is fixed with respect to temperature and to the voltage level of said voltage source Vcc; a pre-charging, p-channel, pull-up transistor, connected between said voltage source Vcc and said input line and activatable during a pre-charge phase of said memory array to raise the voltage level of said input line towards said voltage source; a pull-down transistor of the type of said memory cells connected between said input line and a ground source and activatable after said pre-charge phase to discharge the voltage level of said input line; and a plurality of capacitors selectively connected in parallel to said pull-down transistor, said capacitors defining the speed at which said pull-down transistor discharges said input line.

Claim 10

A PSAD circuit according to claim 6 wherein said means for producing and applying includes: at least one transistor controlled by a reference signal and receiving a voltage source signal as input, wherein said reference signal tracks said voltage source, the at least one transistor producing a second reference current; and a current mirror connected between the output of said at least one transistor and a ground connection of said two transistor inverter for mirroring a version of said second reference current to said ground connection, thereby to produce said first reference current.

Claim 11

A PSAD circuit according to claim 6 and wherein said predetermined amount is defined by the size of said two transistor inverter and the strength of said first reference current.

Claim 12

A PSAD circuit according to claim 6 wherein said first reference current varies with temperature, wherein said two transistor inverter comprises one p-channel transistor and one n-channel transistor, wherein said p-channel transistor is biased to match the temperature variation of said first reference current.