Patent US6069827A successfully refreshed from Google Patents.
US6069827A
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Memory system
Assignee: TORRIDON PLC
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Filing: 1998-03-24
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Granted: 2000-05-30
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Expires: 2018-03-24
Abstract
Abstract A solid state memory for emulating a disk drive comprising: translation means for translating a logical sector address to a main memory address; a main memory composed of non-volatile memory cells erasable in blocks; characterized in that a first pointer is used to point to an unwritten location in main memory, and a second pointer is used to point to the next unerased erasable block in sequence to the erasable block containing the said unwritten memory location; control means being provided to ensure that there is always at least one erasable block in the erased condition between the first and second pointers.
Inventors
- 👤 Alan Welsh Sinclair
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 21:28
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/023; G06F12/0238; G06F12/0246; G06F3/00; G06F3/06; G06F3/0601; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G06F3/0662; G06F3/0664; Y; Y02; Y02D; Y02D10/00
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
173 words
A memory system comprising: a plurality of memory locations each having a pre-defined physical address, said memory locations being arranged in erasable blocks of memory locations; translation means for translating a logical address to one of said predefined physical addresses, means for storing a first pointer that points to a memory location which is to be written to; means for storing a second pointer that points to one of said erasable blocks which is to be erased, said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence of erasable blocks, the predetermined sequence including said memory location to be written to; and control means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence, and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer.
Claim 2
Dependent Claim
173 words
A memory system comprising: a plurality of memory locations each having a pre-defined physical address, said memory locations being arranged in erasable blocks of memory locations; translation means for translating a logical address to one of said predefined physical addresses, means for storing a first pointer that points to a memory location which is to be written to; means for storing a second pointer that points to one of said erasable blocks which is to be erased, said erasable block which is to be erased being the next unerased erasable block in a predetermined sequence of erasable blocks, the predetermined sequence including said memory location to be written to; and control means being provided to progress the first pointer sequentially through the blocks of memory locations in order of said predetermined sequence, and to ensure that there is always at least one erased erasable block in said predetermined sequence of blocks between the erasable block containing said memory location indicated by the first pointer and the erasable block indicated by the second pointer.
Claim 3
Dependent Claim
36 words
A memory system according to claim 1 characterised in that said memory location to be written to is an unwritten memory location having the lowest physical address of all unwritten memory locations in the predetermined sequence.
Claim 4
Dependent Claim
36 words
A memory system according to claim 1 characterised in that said memory location to be written to is an unwritten memory location having the highest physical address of all unwritten memory locations in the predetermined sequence.
Claim 5
Dependent Claim
30 words
A memory system according to claim 1 characterised in that the next unerased erasable block corresponds to an unerased erasable block with the lowest physical address above the first pointer.
Claim 6
Dependent Claim
30 words
A memory system according to claim 1 characterised in that the next unerased erasable block corresponds to an unerased erasable block with the lowest physical address below the first pointer.
Claim 7
Dependent Claim
22 words
A memory system according to claim 1 further including a buffer to increase the speed of writing data to the memory locations.
Claim 8
Dependent Claim
16 words
A memory system according to claim 6 characterised in that said buffer is an SRAM buffer.
Claim 9
Dependent Claim
16 words
A memory system according to claim 6 characterised in that said buffer is a DRAM buffer.
Claim 10
Dependent Claim
20 words
A solid state memory according to claim 1 characterised in that said memory locations are provided in a FLASH EPROM.
Claim 11
Dependent Claim
21 words
A memory system according to claim 1 characterised in that each said memory location comprises a plurality of chalcogenide memory cells.
Claim 12
Dependent Claim
19 words
A memory system according to claim 1 characterised in that said memory locations are provided in a ferro-optic memory.
Claim 13
Dependent Claim
24 words
A memory system according to claim 1 characterised in that said control means is selected from: a microprocessor, a microcontroller, and a state machine.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-30 | 2003-11-29 | 2004-05-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-30 | 2007-11-29 | 2008-05-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-30 | 2011-11-29 | 2012-05-30 | $7700.00 | Window Closed / Lapsed |