EP0619541A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Flash memory control method and information processing system therewith
Assignee: Hitachi Ltd
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Filing: 1994-04-08
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Granted: —
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Expires: 2014-04-08
Abstract
Abstract A control method and system when a flash memory is used as a semiconductor disk or a main memory in an information processing system. A semiconductor file system comprises a first nonvolatile memory electrically erasable, a second nonvolatile memory not electrically erasable, a volatile memory, a controller which controls the memories, and a control section which controls the controller wherein a physical address corresponding to a logical address specified from an external system is accessed. The first nonvolatile memory stores data for the external system to perform operations, first management information indicating the correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of the first nonvolatile memory. The second nonvolatile memory previously stores interface information required for inputting and outputting the data from and to the external system and read-only data of the data. The controller comprises control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from the first nonvolatile memory or when data is input to the volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address. The control section is responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into the first nonvolatile memory from the external system in the volatile memory and then transferring the write data from the volatile memory to the first nonvolatile memory. The consecutive address generation means and the sector address storage means output the physical sector address and the consecutively generated addresses to the first nonvolatile memory and the volatile memory when data at the physical sector address is output from the first nonvolatile memory or when data at the physical sector address is input to the volatile memory.
Inventors
- 👤 Tsunehiro Tobita
- 👤 Jun Kitahara
- 👤 Takashi Tsunehiro
- 👤 Kunihiro Katayama
- 👤 Ryuichi Hattori
- 👤 Yukihiro Seki
- 👤 Hajime Yamagami
- 👤 Takashi Totsuka
- 👤 Takeshi Wada
- 👤 Yosio Takaya
- 👤 Manabu Saito
- 👤 Kenichi Kaki
- 👤 Takao Okubo
- 👤 Takashi Kikuchi
- 👤 Masamichi Kishi
- 👤 Takeshi Suzuki
- 👤 Shigeru Kadowaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 03:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/76; G11C29/765; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1433; G06F11/1441; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0866; G06F3/00; G06F3/06; G06F3/0601; G06F3/0602; G06F3/061; G06F3/0613; G06F3/0614; G06F3/0616; G06F3/0628; G06F3/0638; G06F3/064; G06F3/0644; G06F3/0655; G06F3/0656; G06F3/0668; G06F3/0671; G06F3/0673; G06F3/0679; G06F3/068; G11C29/78; G11C29/785; G11C29/789; G11C29/80; G11C29/816; G11C29/82; G06F2212/00; G06F2212/20; G06F2212/202; G06F2212/2022; G06F2212/31; G06F2212/312; G06F3/0662; G06F3/0664
Claims Analysis
Total Claims: 49
Claim 1
Independent Claim
305 words
A semiconductor file system comprising a first nonvolatile memory which is electrically erasable, a second nonvolatile memory which is not electrically erasable, a volatile memory, a controller which controls said memories, and a control section which controls said controller wherein a physical address corresponding to a logical address specified from an external system is accessed, said first nonvolatile memory storing data for the external system to perform operations, first management information indicating a correspondence between physical addresses at which the data is stored and logical addresses, and second management information indicating a state of said first nonvolatile memory; said second nonvolatile memory previously storing interface information required for inputting and outputting the data from and to the external system and read-only data of the data; said controller including control means for determining a physical sector address forming predetermined high-order bits of the physical address when data is output from said first nonvolatile memory and when data is input to said volatile memory, means for storing the determined physical sector address, and means for consecutively generating addresses in a sector determined by the physical sector address; said control section responsive to the interface information, the first management information, and the second management information for controlling input/output of data from/to the external system and for temporarily storing write data into said first nonvolatile memory from the external system in said volatile memory and then transferring the write data from said volatile memory to said first nonvolatile memory; and said consecutive address generation means and said sector address storage means for outputting the physical sector address and the consecutively generated addresses to said first nonvolatile memory and said volatile memory when data at the physical sector address is output from said first nonvolatile memory and when data at the physical sector address is input to said volatile memory.
Claim 2
Dependent Claim
42 words
A semiconductor file system as claimed in claim 1 wherein when unnecessary data of the data stored in said first nonvolatile memory is erased, said volatile memory temporarily stores necessary data contained in a range in which erasure is to be executed.
Claim 3
Dependent Claim
84 words
A semiconductor file system as claimed in claim 1 further comprising: a plurality of said sector address storage means; said control section storing a next sector address to be accessed in one sector address storage means when a request to consecutively access a plurality of sectors is received from the external system; and means for outputting a signal for another sector address storage means to accept the physical sector address contained in said one sector address storage means after input/output of 1-sector data terminates.
Claim 4
Dependent Claim
82 words
A semiconductor file system as claimed in claim 1 wherein said first management information and said second management information are transferred to said volatile memory, further including: said control section which outputs a predetermined address corresponding to the type of management information when said management information corresponding to said data is accessed; and an address generation section which generates a physical address at which said management information is stored from said predetermined address and a logical sector address corresponding to said data.
Claim 5
Dependent Claim
63 words
A semiconductor file system as claimed in claim 1 further comprising: said control section which accepts an interrupt signal from said controller and performs processing in response to an interrupt source indicated by the interrupt signal; and means for storing the interrupt source, wherein upon acceptance of the interrupt signal, said control section reads the interrupt source from said interrupt source storage means.
Claim 6
Dependent Claim
104 words
A semiconductor file system as claimed in claim 1 further comprising: means for measuring a predetermined time period to control refresh operation of said volatile memory if said volatile memory requires refresh operation; means for counting the number of times refresh operation is executed within said predetermined time period; and means for outputting a refresh control signal, after the number of times the refresh control signal has been output within the predetermined time period measured by said time measurement means reaches a predetermined count, said refresh control signal output means for suppressing another output of the refresh control signal within said predetermined time period.
Claim 7
Dependent Claim
26 words
A semiconductor file system as claimed in claim 1 wherein said interface information provides interface specifications of PCMCIA standard and is provided as an IC card.
Claim 8
Dependent Claim
118 words
A flash memory system comprising: a flash memory storing data from an external system; means for temporarily storing the data from the external system upon receipt of a request to write the data into said flash memory; and a control section which stores the data in said data storage means upon receipt of the request to write the data, then transfers the data to said flash memory, wherein upon receipt of a request to read or write data from the external system before completion of transfer of the data to said flash memory, said control section interrupts the data transfer to said flash memory and responds to the request to read or write data from the external system.
Claim 9
Dependent Claim
83 words
A flash memory system as claimed in claim 8 further comprising: means for storing information indicating whether or not the data is stored in said data storage means, wherein the control section is responsive to the information for determining whether or not the data whose read is requested by the external system is stored in said data storage means and if the information indicates that the data is stored in said data storage means, reads out the data from said data storage means.
Claim 10
Dependent Claim
78 words
A flash memory system as claimed in claim 8 further comprising: means for storing information indicating a correspondence between a logical address specified by the external system and a physical address of said data storage means when the external system accesses the data, wherein if the information indicates that the data whose read is requested by the external system is stored in said data storage means, said control section reads out the data from said data storage means.
Claim 11
Dependent Claim
117 words
A flash memory system as claimed in claim 8 wherein said control section, which upon receipt of a request to read or write data from the external system while transferring data from said data storage means to said flash memory, interrupts the data transfer, has interrupt information storage means for storing information required to restart the interrupted transfer after completion of processing for the request received from the external system, wherein after storing the information in said interrupt information storage means, said control section responds to the data read or write request and after completion of processing for the request, restarts the interrupted data transfer in response to the information stored in said interrupt information storage means.
Claim 12
Dependent Claim
60 words
A flash memory system as claimed in claim 8 wherein upon receipt of a request to write data into a specific area of said flash memory from the external system, said control section performs concurrent processing of storing the write data in said data storage means and erasing unnecessary data previously stored in the specific area of the flash memory.
Claim 13
Dependent Claim
40 words
A flash memory system as claimed in claim 9 wherein after completion of data transfer from said data storage means to said flash memory, said control section transfers the information stored in said information storage means to said flash memory.
Claim 14
Dependent Claim
32 words
A flash memory system as claimed in claim 9 wherein said control section transfers the information stored in said information storage means to said flash memory immediately before power is turned off.
Claim 15
Dependent Claim
59 words
A flash memory system as claimed in claim 13 wherein when the contents of said information storage means are transferred to the flash memory, a location in said flash memory to which the information storage means contents are to be transferred is made variable and information indicating the location is transferred to a predetermined location in said flash memory.
Claim 16
Dependent Claim
132 words
A flash memory system comprising: a flash memory storing data from an external system; means for temporarily storing the data from the external system upon receipt of a request to write the data into said flash memory; and a control section which stores the data in said data storage means upon receipt of the request to write the data, then transfers the data to said flash memory, wherein upon receipt of a new request to write data into the same address from the external system before completion of transfer of the data to said flash memory, said control section interrupts the data transfer to said flash memory and stores the new data from the external system in said data storage means and invalidates the current data being transferred to said flash memory.
Claim 17
Dependent Claim
90 words
A flash memory system comprising: a flash memory storing data from an external system; means for measuring time period required to write the data into said flash memory; means responsive to the measurement result of said write time period measurement means for diagnosing a degradation degree of said flash memory; means for storing the diagnosis result offered by said degradation degree diagnosis means; and control means responsive to the diagnosis result for determining a storage location in said flash memory for the data and storing the data in the location.
Claim 18
Dependent Claim
34 words
A flash memory system as claimed in claim 17 wherein when determining the storage location in said flash memory, said control means references the diagnosis result and selects a location which is less degraded.
Claim 19
Dependent Claim
150 words
A storage system having a semiconductor memory section comprising a storage section using a flash memory as a storage medium and a host system which transfers information to and from said semiconductor memory section, said semiconductor memory section including: an interface circuit transferring information to and from said host system; a control circuit controlling a read/write of information from/into said storage section and detecting an error incurring area of said storage section; and memory management means retaining a used or unused state for each area of said storage section, upon detection of an error by said control circuit, for allocating an unused area as an alternate area in place of the error incurring area of said storage section and retaining a correspondence between the allocated alternate area and the error incurring area, said control circuit referencing said memory management means for controlling a read/write of information from/into said storage section.
Claim 20
Dependent Claim
81 words
A storage system as claimed in claim 19 wherein said control circuit comprises information means, upon detection of an error incurring area of said storage section, for sending error information indicating detection of the error incurring area of said storage section to said host system and said host system comprises means for detecting receipt of the error information from said information means and means for outputting error information upon detection of receipt of the error information by said information detection means.
Claim 21
Dependent Claim
90 words
A storage system as claimed in claim 19 wherein said semiconductor memory section further includes means for retaining predetermined error information; said control circuit, upon detection of an error incurring area of said storage section, sets error information indicating detection of the error occurring area of said storage section in said error information retention means; and said host system comprises detection means for referencing said error information retention means for detecting the error information and means for outputting error information upon detection of the error information by said detection means.
Claim 22
Dependent Claim
46 words
A storage system as claimed in claim 21 wherein said control circuit further detects that no alternate area becomes available in said storage section and further sets error information indicating that no alternate area becomes available in said storage section in said error information retention means.
Claim 23
Dependent Claim
90 words
A storage system as claimed in claim 19 wherein said host system comprises input means for accepting an instruction for previously setting a data area for storing data and the alternate area of said storage section as initialization information and setting means responsive to the instruction accepted through said input means for setting the initialization information in said memory management means and said memory management means is responsive to the setting of said setting means for dividing said storage section into the data area and the alternate area for management.
Claim 24
Dependent Claim
94 words
A storage system as claimed in claim 23 wherein said memory management means comprises reallocation means for detecting an unused block of an empty area of the data area when no further alternate areas are available, and reallocating the detected unused block to the alternate area and reallocation information means for informing said host system that the unused block is set as the alternate area when the block is reallocated by said reallocation means, and the host system inhibits use of the unused block upon receipt of reallocation information from said reallocation information means.
Claim 25
Independent Claim
169 words
A method for controlling storage in a semiconductor memory using a flash memory as a storage medium comprising the steps of: previously retaining a write address corresponding to address information indicated for a write from an external system; retaining a used or unused state of an area indicated by the storage medium write address and upon receipt of a write instruction together with address information from the external system, referencing the previously retained write address corresponding to the address information; writing into the area indicated by the write address; setting the used state for the area at the writing and retaining the state; determining whether or not a write error occurs during writing; if a write error occurs, allocating an unused area as an alternate area in place of the error incurring area and writing into the alternate area; changing the previously retained write address to a write address of the alternate area for updating the write address; and informing the external system that the alternate area is used.
Claim 26
Independent Claim
213 words
A method for controlling storage in a semiconductor memory using a flash memory as a storage medium comprising the steps of: accepting an instruction for dividing a semiconductor memory area into a data area for storing data and an alternate area, when a write error occurs, for allocating an area other than the error incurring area and previously retaining a write address of the data area corresponding to address information and an address of the alternate area in response to the instruction; retaining a used or unused state of the data area and the alternate area for each address; upon receipt of a write instruction together with address information, referencing the previously retained write address corresponding to the address information; writing into the area indicated by the time of write address; setting the used state for the area at the writing and retaining the state; determining whether or not a write error occurs during writing; if a write error occurs, allocating an unused area as an alternate area in place of the error incurring area and writing into the alternate area; changing the previously retained write address to a write address of the alternate area for updating the write address; and setting the used state for the alternate area and retaining the state.
Claim 27
Dependent Claim
247 words
An information processing system comprising a central processing unit, input means for inputting data, output means for outputting data, volatile storage means for storing data, nonvolatile storage means being capable of electrically rewriting stored data to which an address space accessible by said central processing unit is allocated, data control means for at least transferring data between said volatile storage means and said nonvolatile storage means, means for registering addresses of data stored in said volatile storage means in said nonvolatile storage means, and means for comparing the addresses registered in said address registration means with an address output by said central processing unit to make a data access, wherein when the address output by said central processing unit to make a data access is input to said address comparison means and said address comparison means makes a comparison therebetween and outputs a comparison result, said data control means determines whether or not the address is one of the addresses registered in said address registration means in response to the comparison result, and when the address is one of the registered addresses, accesses the registered address in said volatile storage means; in contrast, when the address is not any of the registered addresses, newly registers at least a predetermined range of addresses containing the address in said address registration means, creates a new data storage area corresponding to the newly registered addresses in said volatile storage means, and accesses at least one of the newly registered addresses.
Claim 28
Dependent Claim
20 words
An information processing system as claimed in claim 27 further comprising access history record means for recording access history information.
Claim 29
Dependent Claim
66 words
An information processing system as claimed in claim 28 wherein when said volatile storage means fills with data and does not contain any new data storage area, said data control means references the access history information in said access history record means for detecting an address the last access to which is the oldest among recorded addresses and deletes the address from said address registration means.
Claim 30
Dependent Claim
37 words
An information processing system as claimed in claim 29 wherein said data control means further transfers data in said volatile storage means corresponding to the address deleted from said address registration means to said nonvolatile storage means.
Claim 31
Dependent Claim
23 words
An information processing system as claimed in claim 27 wherein said volatile storage means is made of a ferroelectric random access memory (FRAM).
Claim 32
Dependent Claim
100 words
An information processing system as claimed in claim 27 further comprising power off means started by a power off operation when a power supply given to said system is turned off, save process means responsive to a power off process by said power off means for storing information including contents of internal registers contained in said information processing system and contents of internal registers contained in said input means and output means in some area of said nonvolatile storage means, and means for stopping the power supply to said system upon completion of the process of said save process means.
Claim 33
Dependent Claim
44 words
An information processing system as claimed in claim 27 wherein said data control means further monitors an amount of data stored in said volatile storage means and always reserves a data unstored area having a capacity equal to or greater than a predetermined capacity.
Claim 34
Dependent Claim
91 words
An information processing system as claimed in claim 27 further comprising write inhibit information storage means in which a write inhibit flag can be set indicating that a data write is inhibited for each of blocks into which said nonvolatile storage means is divided, wherein when data is stored in one block of said nonvolatile storage means, if the write inhibit flag is provided corresponding to the block, said data control means outputs a message to the effect that a write request into said block is made to said output means.
Claim 35
Dependent Claim
20 words
An information processing system as claimed in claim 27 wherein said nonvolatile storage means is made of a flash memory.
Claim 36
Dependent Claim
116 words
An information processing system using as a main memory a flash memory, a memory which requires that all data in a write block of the memory should be erased before data from a CPU is written into the block, said information processing system comprising: a cache memory in a copy back system having a plurality of data regions each retaining a copy of block data in a part of said main memory; and control means, when a cache memory hit occurs in write processing into said main memory from said CPU, for updating data in a corresponding data region of said cache memory and performing erasure processing for a corresponding write block of said main memory.
Claim 37
Dependent Claim
45 words
An information processing system as claimed in claim 36 wherein said control means skips the erasure process if the corresponding block of said main memory is already erased even if a cache memory hit occurs in write processing into said main memory from said CPU.
Claim 38
Dependent Claim
60 words
An information processing system as claimed in claim 37 wherein said cache memory has means for retaining erasure information indicating whether or not each block of said main memory whose data copy is retained in said cache memory is already erased and said control means references the erasure information for skipping the erasure process in response to the reference result.
Claim 39
Dependent Claim
74 words
An information processing system as claimed in claim 36 wherein when a cache memory miss occurs in write processing into said main memory from said CPU, if a data region of said cache memory selected to retain a data copy in a write target block of said main memory is not updated, said control means updates the data region with write data and erases data in the write target block of said main memory.
Claim 40
Dependent Claim
58 words
An information processing system as claimed in claim 39 wherein said cache memory has means for retaining update information indicating whether or not data in each data region has been updated by write processing from said CPU and said control means references the update information for erasing the data in the block in response to the reference result.
Claim 41
Dependent Claim
98 words
An information processing system as claimed in claim 36 further including means, when a size of each block of said flash memory and a size of each data region of said cache memory are each m bytes (m being an arbitrary positive integer) and said CPU reads data of a smaller size than m bytes from said main memory, for temporarily reading all data in a block containing the data in said main memory and selecting only the data requested by said CPU among all the data in the block for outputting the selected data to a bus.
Claim 42
Dependent Claim
104 words
An information processing system as claimed in claim 36 wherein when a size of each block of said flash memory and a size of each data region of said cache memory are each m bytes (m being an arbitrary positive integer) and said CPU writes data of a smaller size than m bytes into said main memory, said control means temporarily reads all data in a corresponding block of said main memory and updates the data only in a partial area into which said CPU is to write data, then again writes all the 1-block data into the corresponding block of said main memory.
Claim 43
Dependent Claim
60 words
An information processing system as claimed in claim 42 wherein said cache memory has means for retaining update area information indicating which partial area in each data region has been updated and said control means references the update area information for updating only the partial area into which said CPU is to write data in response to the reference result.
Claim 44
Dependent Claim
40 words
An information processing system as claimed in claim 27 wherein if power of said information processing system is turned off, data in said address registration means is retained at least until power is again supplied to said information processing system.
Claim 45
Dependent Claim
113 words
An information processing system as claimed in claim 44 wherein when operation of said information processing system is restarted by supplying power again after a power supply to said information system is nonentarily stopped, the data retained in said address registration means is referenced and data stored in an area of said nonvolatile storage means that can be specified from the registered address data is transferred to and stored in an area of said volatile storage means that can be specified from a location in which said address registration means stores the address data, thereby restoring storage contents of said volatile storage means to a state when the power supply was nonentarily stopped.
Claim 46
Dependent Claim
80 words
An information processing system as claimed in claim 27 wherein when power of said information processing system is turned off, data in said address registration means is transferred to and stored in a specific location of said nonvolatile storage means for saving the data retained in said address registration means and when a power supply is started again, the saved data is restored in said address registration means, thereby preventing the data in said address registration means from being lost.
Claim 47
Dependent Claim
38 words
An information processing system as claimed in claim 27 wherein data stored in said volatile storage means by a write access from said central processing unit is written back into said nonvolatile storage means every given time period.
Claim 48
Dependent Claim
46 words
An information processing system as claimed in claim 47 wherein data in said address registration means is also saved in said nonvolatile storage means when the data stored in said volatile storage means is written back into said nonvolatile storage means every given period of time.
Claim 49
Dependent Claim
96 words
An information processing system as claimed in claim 27 wherein electrically rewritable nonvolatile storage means containing a serial buffer having a capacity of a plurality of bytes to input/output data from/to an external system is used as said nonvolatile storage means and wherein data of bytes less than the number of storage bytes of said serial buffer is transferred from said nonvolatile storage means to said volatile storage means and data of bytes equal to the number of storage bytes of said serial buffer is transferred from said volatile storage means to said nonvolatile storage means.
References Cited (Backward Citations)
No citation records indexed.
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