US6067248A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory with single-bit and multi-bit modes of operation and method for performing programming and reading operations therein
Assignee: Samsung Electronics Co Ltd
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Filing: 1999-04-12
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Granted: 2000-05-23
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Expires: 2019-04-12
Abstract
Abstract A nonvolatile memory having a memory field and a redundant field within a single semiconductor chip is disclosed. The memory field is provided to store normal data and the redundant field is provided to store essential device data. The nonvolatile memory includes a plurality of first page buffers performing a multi-bit reading operation for the memory field and a plurality of second page buffers performing a regular single-bit operation for the redundant field. A time period of the regular single-bit operation for the redundant field is shorter than that of the multi-bit operation for the memory field. The nonvolatile semiconductor memory of the invention is therefore capable of performing single-bit operation at a higher speed than the conventional nonvolatile semiconductor memories each having the single- and multi-bit operation modes, improving their performance.
Inventors
- 👤 Tae-Hwa Yoo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 19:19
CPC Classifications
G; G11; G11C; G11C29/00; G11C16/00; G11C16/02; G11C16/04; G11C16/0483; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C11/5642; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5641; G11C2211/5642
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
125 words
A nonvolatile semiconductor memory comprising: a nonvolatile memory cell array having a memory field which is used to store normal data, and a redundant field which is used to store device data on device formulation or address mapping; a page buffer circuit including a plurality of first page buffers coupled to the memory field and a plurality of second page buffers to the redundant field, the first page buffers performing a multi-bit operation for the memory field, and the second page buffers performing a single-bit operation for the redundant field; and a control logic for controlling the operations of the memory field and the redundant field, wherein the control logic makes a time period of the single-bit operation shorter than that of the multi-bit operation.
Claim 2
Dependent Claim
125 words
A nonvolatile semiconductor memory comprising: a nonvolatile memory cell array having a memory field which is used to store normal data, and a redundant field which is used to store device data on device formulation or address mapping; a page buffer circuit including a plurality of first page buffers coupled to the memory field and a plurality of second page buffers to the redundant field, the first page buffers performing a multi-bit operation for the memory field, and the second page buffers performing a single-bit operation for the redundant field; and a control logic for controlling the operations of the memory field and the redundant field, wherein the control logic makes a time period of the single-bit operation shorter than that of the multi-bit operation.
Claim 3
Dependent Claim
21 words
The memory of claim 1, wherein the redundant field comprises a plurality of strings configured in a NAND-type flash memory arrangement.
Claim 4
Dependent Claim
24 words
The memory of claim 1, wherein the page buffer circuit performs programming and reading operations for both the memory field and the redundant field.
Claim 5
Independent Claim
101 words
A method for performing operations in a nonvolatile semiconductor memory having both a multi-bit memory field storing normal data and a single-bit memory field storing device data, the method comprising: determining whether an input command is a device data program/read command or not; performing a multi-bit programming/reading operation on the memory field when the input command is not the device program/read command; and performing a regular single-bit programming/reading operation on the single-bit memory field when the input command is the device program/read command, wherein the regular single-bit programming/reading operation has a time period shorter than that of the multi-bit programming/reading operation.
Claim 6
Independent Claim
101 words
A method for performing operations in a nonvolatile semiconductor memory having both a multi-bit memory field storing normal data and a single-bit memory field storing device data, the method comprising: determining whether an input command is a device data program/read command or not; performing a multi-bit programming/reading operation on the memory field when the input command is not the device program/read command; and performing a regular single-bit programming/reading operation on the single-bit memory field when the input command is the device program/read command, wherein the regular single-bit programming/reading operation has a time period shorter than that of the multi-bit programming/reading operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |