US5966326A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Nonvolatile semiconductor memory equipped with single bit and multi-bit cells
Assignee: Samsung Electronics Co Ltd
•
Filing: 1997-09-12
•
Granted: 1999-10-12
•
Expires: 2017-09-12
Abstract
Abstract A nonvolatile semiconductor memory having a single bit cell array and a multi-bit cell array formed on a substrate of the memory is provided. The memory includes a plurality of memory blocks that correspond to the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the single bit cell array is coupled to a plurality of page buffers. The multi-bit cell array includes a plurality of memory blocks in which one of the blocks corresponds to a plurality of the input/output lines and is divided into a plurality of pages. A plurality of bit lines of the multi-bit cell array is coupled to a plurality of page buffers, A timing controller arranges the processing operations in the two arrays.
Inventors
- 👤 Jong-wook Park
- 👤 Kang-deok Seo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:44
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C11/00; G11C11/56; G11C11/5621; G11C11/5628; G11C16/04; G11C16/0483; G11C16/32; G11C2211/00; G11C2211/56; G11C2211/564; G11C2211/5641; G11C2211/5642
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
143 words
A nonvolatile memory comprising: a plurality of input/output lines; a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit memory blocks, each single-bit memory block being coupled to an input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers; and a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block being coupled to one or more input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers.
Claim 2
Dependent Claim
143 words
A nonvolatile memory comprising: a plurality of input/output lines; a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit memory blocks, each single-bit memory block being coupled to an input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers; and a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block being coupled to one or more input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers.
Claim 3
Dependent Claim
37 words
A nonvolatile memory as recited in claim 1 further comprising a row address detector configured to determine which of the single bit cell array and the multi-bit cell array will receive a received a particular row address.
Claim 4
Dependent Claim
19 words
A nonvolatile memory as recited in claim 2 wherein said row address detector is integral with the nonvolatile memory.
Claim 5
Dependent Claim
19 words
A nonvolatile memory as recited in claim 2 wherein said row address detector is external to the nonvolatile memory.
Claim 6
Dependent Claim
26 words
A nonvolatile memory as recited in claim 1 including a single bit timing controller coupled to the row address detector for controlling the single-bit cell array.
Claim 7
Dependent Claim
25 words
A nonvolatile memory as recited in claim 5 including a multi-bit timing controller coupled to the row address detector for controlling the multi-bit cell array.
Claim 8
Dependent Claim
177 words
A nonvolatile memory, comprising: a plurality of input/output lines; a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit cell memory blocks, each single-bit cell memory block coupled to a respective input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers; and a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block coupled to at least one respective input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers; and a timing controller coupled to the single bit and multi bit cell arrays for generating control signals necessary to arrange processing operations in the plurality of single-bit and multi-bit page buffers.
Claim 9
Dependent Claim
177 words
A nonvolatile memory, comprising: a plurality of input/output lines; a single bit cell array having a plurality of single-bit cell bit lines and a plurality of single-bit cell memory blocks, each single-bit cell memory block coupled to a respective input/output line and being divided into a plurality of single-bit cell pages having a plurality of single-bit cell page buffers, the plurality of single-bit cell bit lines being coupled to the plurality of single-bit cell page buffers; and a multi-bit cell array having a plurality of multi-bit cell bit lines and a plurality of multi-bit cell memory blocks, each multi-bit cell memory block coupled to at least one respective input/output lines and being divided into a plurality of multi-bit cell pages having a plurality of multi-bit cell page buffers, the plurality of multi-bit cell bit lines being coupled to the plurality of multi-bit cell page buffers; and a timing controller coupled to the single bit and multi bit cell arrays for generating control signals necessary to arrange processing operations in the plurality of single-bit and multi-bit page buffers.
Claim 10
Dependent Claim
36 words
A nonvolatile memory as recited in claim 7 including a row address detector configured to determine which of the single bit cell array and the multi-bit cell array will receive a received a particular row address.
Claim 11
Dependent Claim
19 words
A nonvolatile memory as recited in claim 8 wherein said row address detector is integral with the nonvolatile memory.
Claim 12
Dependent Claim
19 words
A nonvolatile memory as recited in claim 8 wherein the row address detector is external to the nonvolatile memory.
Claim 13
Independent Claim
101 words
A method for operating a nonvolatile memory, comprising the steps of: a row address detector receiving from a row address buffer a memory address which is located in one of a single bit cell array and a multi-bit cell array which are formed on a single substrate; the row address detector determining whether the address is in one of the single bit cell array and the multi-bit cell array; the row address detector processing a signal to one of a single bit timing controller and a multi-bit timing controller to access one of the single bit array and the multi-bit array.
Claim 14
Independent Claim
101 words
A method for operating a nonvolatile memory, comprising the steps of: a row address detector receiving from a row address buffer a memory address which is located in one of a single bit cell array and a multi-bit cell array which are formed on a single substrate; the row address detector determining whether the address is in one of the single bit cell array and the multi-bit cell array; the row address detector processing a signal to one of a single bit timing controller and a multi-bit timing controller to access one of the single bit array and the multi-bit array.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-10-11 | 2003-04-12 | 2003-10-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-10-11 | 2007-04-12 | 2007-10-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-10-11 | 2011-04-12 | 2011-10-12 | $7700.00 | Window Closed / Lapsed |