Semiconductor memory device having multilevel memory cell array

Claim 2

A semiconductor memory device comprising: a multilevel memory cell array having a plurality of multilevel memory cells, each of said cells storing data of at least three bits, a regular memory cell array having a plurality of regular memory cells, each of said regular memory cells storing data of two bits, a first X decoder selecting a word line of said multilevel memory cell array corresponding to an input address, a second X decoder selecting a word line of said regular memory cell array corresponding to said input address, a pulse generator circuit generating a plurality of pulse signals with mutually different active periods, a voltage generator circuit generating a control signal having a voltage which varies in response to said plurality of pulses, said control signal being supplied to the selected word line of said multilevel memory cell array, selecting means for selecting a bit line of one of said regular memory cell array and said multilevel memory cell array in response to said input address, and an amplifier circuit outputting a level of said selected bit line after amplifying it.

Claim 3

A semiconductor memory device as claimed in claim 1, wherein said amplifier circuit includes a first sense amplifier, a first switch installed between the output end of said selecting means and said first sense amplifier, a plurality of second sense amplifiers to which are supplied respective members of said plurality of pulse signals, and a signal converter circuit receiving the outputs of said plurality of second sense amplifiers to convert them to two-bit data.

Claim 4

A semiconductor memory device as claimed in claim 1, wherein said pulse generator circuit includes a memory circuit and an output circuit reading data of said memory circuit in response to an address information and outputting the read data as said plurality of pulses.

Claim 5

A semiconductor memory device comprising: a bit line, a power supply line laid parallel to said bit line, a plurality of memory transistors arranged in parallel to one another between said bit line and said power supply line, and a plurality of word lines connected to the gates of said plurality of memory transistors, wherein said bit line and said power supply line are each divided into a first and a second region, said plurality of memory transistors arranged within said first region being regular memory transistors and said plurality of memory transistors arranged within said second region being multilevel memory transistors.

Claim 6

A semiconductor memory device comprising: a bit line, a power supply line laid parallel to said bit line, a plurality of memory transistors arranged in parallel to one another between said bit line and said power supply line, and a plurality of word lines connected to the gates of said plurality of memory transistors, wherein said bit line and said power supply line are each divided into a first and a second region, said plurality of memory transistors arranged within said first region being regular memory transistors and said plurality of memory transistors arranged within said second region being multilevel memory transistors.

Claim 7

A semiconductor memory device as claimed in claim 4 further comprising a selector circuit formed at one end of said bit line, a first sense amplifier circuit for amplifying a first output of said selector circuit, and a second sense amplifier circuit for amplifying a second output of said selector circuit.

Claim 8

A semiconductor memory device comprising, a first transistor either one of the source or the drain thereof being connected to either one of the source or the drain of a multilevel cell, a second transistor either one of the source or the drain thereof being connected to the other of the source or he drain of said multilevel cell, a third transistor either one of the source of the drain thereof being connected to either one of the source or the drain of a regular cell, and the other of the source or the drain thereof being connected to the other of the source or the drain of said first transistor, a fourth transistor either one of the source or the drain thereof being connected to the other of the source or the drain of said regular cell, and the other of the source or the drain thereof being connected to the other of the source or the drain of said second transistor, a constant power supply connected to said other one of the source or the drain of said second transistor, and a digit line connected to said other one of the source or the drain of said first transistor, wherein said first and second transistors are activated and made electrically conductive when reading out data of said multilevel memory cell to said digit line, and said third and fourth transistors are activated and made electrically conductive when reading out data of said regular memory cell to said digit line.

Claim 9

A semiconductor memory device comprising, a first transistor either one of the source or the drain thereof being connected to either one of the source or the drain of a multilevel cell, a second transistor either one of the source or the drain thereof being connected to the other of the source or he drain of said multilevel cell, a third transistor either one of the source of the drain thereof being connected to either one of the source or the drain of a regular cell, and the other of the source or the drain thereof being connected to the other of the source or the drain of said first transistor, a fourth transistor either one of the source or the drain thereof being connected to the other of the source or the drain of said regular cell, and the other of the source or the drain thereof being connected to the other of the source or the drain of said second transistor, a constant power supply connected to said other one of the source or the drain of said second transistor, and a digit line connected to said other one of the source or the drain of said first transistor, wherein said first and second transistors are activated and made electrically conductive when reading out data of said multilevel memory cell to said digit line, and said third and fourth transistors are activated and made electrically conductive when reading out data of said regular memory cell to said digit line.

Claim 10

A semiconductor memory device comprising: a multilevel cell connected to a digit line through a gating transistor, a voltage converting circuit which varies the gate voltage of the multilevel cell, a plurality of comparators each equipped with a first and a second input ends, having said first input ends supplied with a reference voltage and said second input ends connected in common to said digit line, and each comparator outputting a result of comparison of the voltages of said first and second input ends, and a signal converter which receives the output results of said plurality of comparators to convert said output results into corresponding data of specified number of bits, wherein for reading out data of said multilevel cell, said gating means electrically connects the digit line to said multilevel cell, said voltage converting circuit sequentially varies said gate voltage, and said plurality of comparators are alternatively activated sequentially whenever said gate voltage is changed.

Claim 11

A semiconductor memory device comprising: a multilevel cell connected to a digit line through a gating transistor, a voltage converting circuit which varies the gate voltage of the multilevel cell, a plurality of comparators each equipped with a first and a second input ends, having said first input ends supplied with a reference voltage and said second input ends connected in common to said digit line, and each comparator outputting a result of comparison of the voltages of said first and second input ends, and a signal converter which receives the output results of said plurality of comparators to convert said output results into corresponding data of specified number of bits, wherein for reading out data of said multilevel cell, said gating means electrically connects the digit line to said multilevel cell, said voltage converting circuit sequentially varies said gate voltage, and said plurality of comparators are alternatively activated sequentially whenever said gate voltage is changed.