Semiconductor memory having mask ROM that can be set to plurality of threshold levels

Claim 2

A semiconductor memory device comprising at least one word line, at least one memory transistor having a gate connected to said word line and a threshold level selected from a plurality of reference threshold levels, a plurality of comparison transistors each having a gate connected to said word line and a threshold level selected from said reference threshold levels, the threshold levels of said comparison transistors being different from each other, a driving circuit driving said word line with respective ones of driving voltages, at least one of said comparison transistors being rendered conductive each time said word line is driven with either one of said driving voltages, said memory transistor being rendered conductive when said word line is driven with such a driving voltage that exceeds the threshold level of said memory transistor, and means coupled to said memory transistor and said comparison transistors for generating output data consisting of a plurality of bits representative of the threshold level of said memory transistor in response to conductive and non-conductive states of said memory transistor and said comparison transistors.

Claim 3

The device as claimed in claim 1, wherein said driving circuit includes a timing signal generator generating in sequence a plurality of timing signals and a driver driving said word line with each of said driving voltages in response to an associated one of said timing signals.

Claim 4

The device as claimed in claim 2, wherein said means includes a switching circuit selecting each of said comparison transistors in response to an associated one of said timing signals, a current circuit responding to a first current relative to a current flowing through said memory transistor and a second current relative to a current flowing through one of said comparison transistors selected by said switching circuit and producing a logic level, and a data generator responding to said logic level and generating said output data.

Claim 5

The device as claimed in claim 3, wherein said current circuit comprises a current mirror circuit, said current mirror circuit including an output transistor coupled to said memory transistor and a plurality of input transistors coupled to said comparison transistors, respectively, and said switching circuit includes a plurality of switching transistors each coupled between said output transistor and an associated one of said input transistors and rendered conductive in response to an associated one of said timing signals.

Claim 6

The device as claimed in claim 3, wherein said current circuit includes an output transistor coupled to said memory transistor and an input transistor coupled to said output transistor, and said switching circuit includes a plurality of switching transistors each coupled between said input transistor and an associated one of said comparison transistors and rendered conductive in response to an associated one of said timing signals.

Claim 7

The device as claimed in claim 2, wherein said means includes a current mirror circuit having an input node coupled to said memory transistor and a plurality of output nodes coupled to said comparison transistors, respectively, and a logic circuit coupled to said output nodes to generate said output data.

Claim 8

A semiconductor memory comprising at least one word line, at least one memory transistor having a gate connected to said word line and a threshold level selected from a plurality of reference threshold levels, a plurality of comparison transistors having respective gates connected to said word line, each of said comparison transistors having a threshold level selected from said reference threshold levels and the threshold levels of said comparison transistors being different from each other, a voltage driving circuit driving said word line with respective ones of a plurality of driving voltages, and a sensing circuit connected to said memory transistor and said comparison transistors which holds the logical level state based on the difference between the current flowing in said memory transistor and the current flowing in said transistor circuit whenever driving to respective values of said plurality of voltages takes place, and outputs multibit data stored in said memory transistor based on the logical level state held.

Claim 9

A semiconductor memory comprising at least one word line, at least one memory transistor having a gate connected to said word line and a threshold level selected from a plurality of reference threshold levels, a plurality of comparison transistors having respective gates connected to said word line, each of said comparison transistors having a threshold level selected from said reference threshold levels and the threshold levels of said comparison transistors being different from each other, a voltage driving circuit driving said word line with respective ones of a plurality of driving voltages, and a sensing circuit connected to said memory transistor and said comparison transistors which holds the logical level state based on the difference between the current flowing in said memory transistor and the current flowing in said transistor circuit whenever driving to respective values of said plurality of voltages takes place, and outputs multibit data stored in said memory transistor based on the logical level state held.

Claim 10

The semiconductor memory as claimed in claim 7, wherein said voltage driving circuit selects one of a plurality of potentials generated from a potential generating circuit by a timing signal and outputs the selected potential when a specified level is formed by the combination of addresses.

Claim 11

The semiconductor memory as claimed in claim 8, wherein said potential generating circuit comprises an output terminal, a current source connected to a first voltage source terminal and to said output terminal, and a plurality of level shift circuits, each of said level shift circuits connected to said output terminal and to a second voltage source terminal.

Claim 12

The semiconductor memory as claimed in claim 8, wherein said timing signal is produced by a pulse generating circuit comprising nth timing signal producing circuit coupled in series (n being integer that is 2 or more), said 2nd and more timing signal producing circuit inputting an input signal and outputting said timing signal and an output signal, said timing signal changing from a first level to a second level by inputting said input signal and changing from said second level to said first level by changing said output signal from said second level to said first level, said output signal changing from said second level to said first level after a predetermined period since said timing signal changes from said first level to said second level and changing from said first level to said second level after said predetermined period since said timing signal changes from said second level to said first level, said 1st signal producing circuit inputting an ATD signal generated by detecting a change in the address as said input signal.

Claim 13

The semiconductor memory as claimed in claim 10, wherein said signal producing circuit comprises a flip flop inputting said output signal thereof and an output signal of a previous signal producing circuit, a delay circuit inputting an output of said flip flop, an and inverter inputting an output of said delay circuit and outputting said second signal.

Claim 14

The semiconductor memory as claimed in claim 7, wherein said sensing circuit is constituted of a current mirror circuit having unequal input and output currents which uses a transistor on the side of said memory transistor as an input or output and uses correspondingly a transistor on the side of said comparison transistor as an output or input.

Claim 15

The semiconductor memory as claimed in claim 12, wherein said current mirror circuit comprises a first transistor whose source is connected to said memory transistor, and a second transistor whose source is connected to said comparison transistor and forming a ratio of channel length and channel width different from that of said memory transistor.

Claim 16

A semiconductor memory comprising at least one word line, at least one memory transistor having a gate connected to said word line and a threshold level selected from a plurality of reference threshold levels, a plurality of comparison transistors having respective gates connected to said word line, each of said comparison transistors having a threshold level selected from said reference threshold levels and the threshold levels of said comparison transistors being different from each other, a first virtual ground line connected to one of the drain and source of said comparison transistor, a sense line connected to the other of the drain and source of said comparison transistor, a bit line connected to one of the drain and source of said memory transistor, a second virtual ground line connected to the other of the drain and source of said memory transistor, a voltage driving circuit respectively driving said first and second virtual ground lines with respective ones of a plurality of driving voltages, and sensing means consisting of current mirror circuits using said bit line and respective members of said plurality of sense lines as the inputs and outputs, holding the logical level state based on the difference between the current flowing in said memory transistors and the current flowing in said transistor circuit whenever said first and second virtual ground lines drive to respective ones of said plurality of voltages, and outputting multibit data stored in said memory transistors based on the logical level state held.

Claim 17

A semiconductor memory comprising at least one word line, at least one memory transistor having a gate connected to said word line and a threshold level selected from a plurality of reference threshold levels, a plurality of comparison transistors having respective gates connected to said word line, each of said comparison transistors having a threshold level selected from said reference threshold levels and the threshold levels of said comparison transistors being different from each other, a first virtual ground line connected to one of the drain and source of said comparison transistor, a sense line connected to the other of the drain and source of said comparison transistor, a bit line connected to one of the drain and source of said memory transistor, a second virtual ground line connected to the other of the drain and source of said memory transistor, a voltage driving circuit respectively driving said first and second virtual ground lines with respective ones of a plurality of driving voltages, and sensing means consisting of current mirror circuits using said bit line and respective members of said plurality of sense lines as the inputs and outputs, holding the logical level state based on the difference between the current flowing in said memory transistors and the current flowing in said transistor circuit whenever said first and second virtual ground lines drive to respective ones of said plurality of voltages, and outputting multibit data stored in said memory transistors based on the logical level state held.

Claim 18

The semiconductor memory as claimed in claim 14, wherein said voltage driving circuit selects one of a plurality of potentials generated from a potential generating circuit by a timing signal and outputs the selected potential when a specified level is formed by the combination of addresses.

Claim 19

The semiconductor memory as claimed in claim 15, wherein said timing signal is produced by a pulse generating circuit comprising nth timing signal producing circuit coupled in series (n being integer that is 2 or more), said 2nd and more timing signal producing circuit inputting an input signal and outputting said timing signal and an output signal, said timing signal changing from a first level to a second level by inputting said input signal and changing from said second level to said first level by changing said output signal from said second level to said first level, said output signal changing from said second level to said first level after a predetermined period since said timing signal changes from said first level to said second level and changing from said first level to said second level after said predetermined period since said timing signal changes from said second level to said first level, said 1st signal producing circuit inputting an ATD signal generated by detecting a change in the address as said input signal.

Claim 20

The semiconductor memory as claimed in claim 15, wherein said potential generating circuit comprises an output terminal, a current source connected to a first voltage source terminal and to said output terminal, and a plurality of level shift circuits, each of said level shift circuits connected to said output terminal and to a second voltage source terminal.

Claim 21

The semiconductor memory as claimed in claim 14, wherein said sensing circuit is constituted of a current mirror circuit having unequal input and output currents which uses a transistor on the side of said memory transistor as an input or output and uses correspondingly a transistor on the side of said comparison transistor as an output or input.

Claim 22

The semiconductor memory as claimed in claim 18, wherein said current mirror circuit comprises a first transistor whose source is connected to said memory transistor, a second transistor and whose source is connected to said comparison transistor and producing a ratio of channel length and channel width different from that of said memory transistor.

Claim 23

The semiconductor memory as claimed in claim 14, wherein said sensing means further comprises a sensing circuit comparing the potential of said bit line with the potential of said sense line, and outputs a signal of a first logical level when the potential of said bit line is higher than the potential of said sense line and outputs a signal of a second logical level when the potential of said bit line is lower than the potential of said sense line.