US6066562A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for fabricating silicon semiconductor discrete wafer
Assignee: Naoetsu Electronics Co Ltd
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Filing: 1997-07-22
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Granted: 2000-05-23
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Expires: 2017-07-22
Abstract
Abstract A method of fabricating a silicon semiconductor discrete wafer is disclosed that assures excellent finishing accuracy and productivity. The method for fabricating a discrete wafer having a double-layer structure including an impurity diffused layer at one side and an impurity non-diffused layer at the opposite side includes cutting a wafer, having one of the impurity diffused layers formed on both surfaces of the silicon semiconductor wafer and having an oxide film formed on the surface of the diffused layer, into two pieces at the center of thickness with an ID saw slicing machine. Then, both surfaces of the cutting surface are ground to a predetermined thickness with a surface grinding machine, and the grinding surfaces are lapped with abrasive grains having a count of at least #2000 and no more than #6000. The processing surface is wet-etched as the final processing.
Inventors
- 👤 Hisashi Ohshima
- 👤 Tsutomu Satoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 12:46
CPC Classifications
H; H10; H10P; H10P52/00; H10P90/00; H10P90/12; H10P90/123; B; B24; B24B; B24B37/00; B24B37/04; B24B7/00; B24B7/20; B24B7/22; B24B7/228; B28; B28D; B28D5/00; B28D5/02; B28D5/022; B28D5/028; H10P50/00
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
154 words
A method of fabricating silicon semiconductor discrete wafer of a double-layer structure, said method comprising: cutting a diffused wafer into two pieces at the center of the wafer thickness, each piece having an impurity diffused layer at one side and an impurity non-diffused layer at a cutting surface on the other side thereof, then grinding both cutting surfaces with an abrasive grain of a count no less than #2000 and no greater than #6000, then wet etching both ground surfaces, both wet etched surfaces being completed by the wet etching; collecting grinding water including silicon semiconductor chips during the grinding; mixing air into the grinding water, and jetting the mixed grinding water, during the grinding, as a group of minute grinding water drops, to a grinding wheel surface of a grinding wheel with said abrasive grain of a count no less than #2000 and no greater than #6000, thereby dressing the grinding wheel surface.
Claim 2
Independent Claim
154 words
A method of fabricating silicon semiconductor discrete wafer of a double-layer structure, said method comprising: cutting a diffused wafer into two pieces at the center of the wafer thickness, each piece having an impurity diffused layer at one side and an impurity non-diffused layer at a cutting surface on the other side thereof, then grinding both cutting surfaces with an abrasive grain of a count no less than #2000 and no greater than #6000, then wet etching both ground surfaces, both wet etched surfaces being completed by the wet etching; collecting grinding water including silicon semiconductor chips during the grinding; mixing air into the grinding water, and jetting the mixed grinding water, during the grinding, as a group of minute grinding water drops, to a grinding wheel surface of a grinding wheel with said abrasive grain of a count no less than #2000 and no greater than #6000, thereby dressing the grinding wheel surface.
Claim 3
Independent Claim
159 words
A method of fabricating silicon semiconductor discrete wafer of a double-layer structure, said method comprising: cutting a diffused wafer into two pieces at the center of the wafer thickness, each piece having an impurity diffused layer at one side and an impurity non-diffused layer at a cutting surface on the other side thereof, then grinding both cutting surfaces, then lapping both cutting surfaces with an abrasive grain of a count no less than #2000 and no greater than #6000, then wet etching both lapped surfaces, both wet etched surfaces being completed by the wet etching collecting grinding water including silicon semiconductor chips during the grinding; mixing air into the grinding water, and jetting the mixed grinding water, during the grinding, as a group of minute grinding water drops, to a grinding wheel surface of a grinding wheel with said abrasive grain of a count no less than #2000 and no greater than #6000, thereby dressing the grinding wheel surface.
Claim 4
Independent Claim
159 words
A method of fabricating silicon semiconductor discrete wafer of a double-layer structure, said method comprising: cutting a diffused wafer into two pieces at the center of the wafer thickness, each piece having an impurity diffused layer at one side and an impurity non-diffused layer at a cutting surface on the other side thereof, then grinding both cutting surfaces, then lapping both cutting surfaces with an abrasive grain of a count no less than #2000 and no greater than #6000, then wet etching both lapped surfaces, both wet etched surfaces being completed by the wet etching collecting grinding water including silicon semiconductor chips during the grinding; mixing air into the grinding water, and jetting the mixed grinding water, during the grinding, as a group of minute grinding water drops, to a grinding wheel surface of a grinding wheel with said abrasive grain of a count no less than #2000 and no greater than #6000, thereby dressing the grinding wheel surface.
Claim 5
Independent Claim
140 words
A method of fabricating a silicon semiconductor discrete wafer of a double-layer structure having an impurity diffused layer on one side of the silicon semiconductor wafer and an impurity non-diffused layer on the opposite side thereof, comprising slicing the silicon semiconductor wafer, on both sides of which an impurity diffused layer has been formed, into two pieces at the center of the wafer thickness, characterized in that the slicing of the wafer into two pieces is carried out after an oxide layer has been further formed on the diffused layers on both surfaces of the wafer; that only the sliced surface side is finally lapped with abrasive grains of the size number #2000 or greater but #6000 or smaller; and that the resultant wafer is immersed in an etching solution of a mixed acid thereby to finish said lapped surface.
Claim 6
Independent Claim
140 words
A method of fabricating a silicon semiconductor discrete wafer of a double-layer structure having an impurity diffused layer on one side of the silicon semiconductor wafer and an impurity non-diffused layer on the opposite side thereof, comprising slicing the silicon semiconductor wafer, on both sides of which an impurity diffused layer has been formed, into two pieces at the center of the wafer thickness, characterized in that the slicing of the wafer into two pieces is carried out after an oxide layer has been further formed on the diffused layers on both surfaces of the wafer; that only the sliced surface side is finally lapped with abrasive grains of the size number #2000 or greater but #6000 or smaller; and that the resultant wafer is immersed in an etching solution of a mixed acid thereby to finish said lapped surface.
Claim 7
Independent Claim
141 words
A method of fabricating a silicon semiconductor discrete wafer of a double-layer structure having an impurity diffused layer on one side of the silicon semiconductor wafer and an impurity non-diffused layer on the opposite side thereof, comprising slicing the silicon semiconductor wafer, on both sides of which an impurity diffused layer has been formed, into two pieces at the center of the wafer thickness, characterized in that the slicing of the wafer into two pieces is carried out after an oxide layer has been further formed on the diffused layers on both surfaces of the wafer; that only the sliced surface side is finally ground with a grinding stone of the size number #2000 or greater but #6000 or smaller; and that the resultant wafer is immersed in an etching solution of a mixed acid thereby to finish said ground surface.
Claim 8
Independent Claim
141 words
A method of fabricating a silicon semiconductor discrete wafer of a double-layer structure having an impurity diffused layer on one side of the silicon semiconductor wafer and an impurity non-diffused layer on the opposite side thereof, comprising slicing the silicon semiconductor wafer, on both sides of which an impurity diffused layer has been formed, into two pieces at the center of the wafer thickness, characterized in that the slicing of the wafer into two pieces is carried out after an oxide layer has been further formed on the diffused layers on both surfaces of the wafer; that only the sliced surface side is finally ground with a grinding stone of the size number #2000 or greater but #6000 or smaller; and that the resultant wafer is immersed in an etching solution of a mixed acid thereby to finish said ground surface.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-23 | 2003-11-22 | 2004-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-23 | 2007-11-22 | 2008-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-23 | 2011-11-22 | 2012-05-23 | $7700.00 | Window Closed / Lapsed |