Patent US6065085A successfully refreshed from Google Patents.
US6065085A
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Bus bridge architecture for a data processing system capable of sharing processing load among a plurality of devices
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1998-01-27
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Granted: 2000-05-16
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Expires: 2018-01-27
Abstract
Abstract The method and apparatus provides a data processing system. The data processing system includes a primary bus, a secondary bus, and a host processor connected to the primary bus. The data processing system includes a first secondary processor connected to the primary bus and the secondary bus. Additionally, a second secondary processor is connected to the secondary bus. The first secondary processor and the second secondary processor forms cascaded processors for input/output functions. Selected functions normally performed by the second secondary processor are performed by the first secondary processor, wherein a division of workload increases performance of the data processing system. This architecture allows shifting of workload down to the secondary bus.
Inventors
- 👤 Louis H. Odenwald, Jr.
- 👤 Steven R. Schremmer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 15:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/40; G06F13/4004; G06F13/4027
Claims Analysis
Total Claims: 31
Claim 1
Independent Claim
112 words
A data processing system comprising: a primary bus; a secondary bus; a host processor connected to the primary bus; a first secondary processor connected to the primary bus and the secondary bus, wherein the first secondary bus processor provides communication between the primary bus and the secondary bus; and a second secondary processor connected to the secondary bus, wherein a plurality of functions are performed by the second secondary processor and wherein a portion of the functions within the plurality of functions are assigned to the first secondary processor for performance by the first secondary processor such that performance of the portion of the functions by the second secondary processor is absent.
Claim 2
Dependent Claim
112 words
A data processing system comprising: a primary bus; a secondary bus; a host processor connected to the primary bus; a first secondary processor connected to the primary bus and the secondary bus, wherein the first secondary bus processor provides communication between the primary bus and the secondary bus; and a second secondary processor connected to the secondary bus, wherein a plurality of functions are performed by the second secondary processor and wherein a portion of the functions within the plurality of functions are assigned to the first secondary processor for performance by the first secondary processor such that performance of the portion of the functions by the second secondary processor is absent.
Claim 3
Dependent Claim
23 words
The data processing system of claim 1, wherein the primary bus is a PCI bus and the secondary bus is a PCI bus.
Claim 4
Dependent Claim
17 words
The data processing system of claim 1, wherein the first secondary processor is within an input/output platform.
Claim 5
Dependent Claim
17 words
The data processing system of claim 3, wherein the second secondary processor is within an input/output platform.
Claim 6
Dependent Claim
25 words
The data processing system of claim 1, wherein the data processing system is an intelligent input/output data processing system under an intelligent input/output architecture specification.
Claim 7
Dependent Claim
17 words
The data processing system of claim 1, wherein the first secondary processor is within an input/output platform.
Claim 8
Dependent Claim
17 words
The data processing system of claim 6, wherein the second secondary processor is within an input/output platform.
Claim 9
Dependent Claim
141 words
A data processing system comprising: a primary bus; a secondary bus; a host processor connected to the primary bus; a first secondary processor connected to the primary bus and the secondary bus, wherein the first secondary processor provides communication between the primary bus and the secondary bus; a second secondary processor connected to the secondary bus; and wherein a first device driver and a second device driver define functions performed by the second secondary processor within an input/output platform and wherein the first device driver is loaded on an input/output platform containing the first secondary processor and the second device driver is loaded on the input/output platform containing the second secondary processor such that the first secondary processor performs a function defined by the first device driver and the second secondary processor performs a function defined by the second device driver.
Claim 10
Dependent Claim
141 words
A data processing system comprising: a primary bus; a secondary bus; a host processor connected to the primary bus; a first secondary processor connected to the primary bus and the secondary bus, wherein the first secondary processor provides communication between the primary bus and the secondary bus; a second secondary processor connected to the secondary bus; and wherein a first device driver and a second device driver define functions performed by the second secondary processor within an input/output platform and wherein the first device driver is loaded on an input/output platform containing the first secondary processor and the second device driver is loaded on the input/output platform containing the second secondary processor such that the first secondary processor performs a function defined by the first device driver and the second secondary processor performs a function defined by the second device driver.
Claim 11
Dependent Claim
17 words
The data processing system of claim 8, wherein the first device driver is an intermediate service module.
Claim 12
Dependent Claim
17 words
The data processing system of claim 9, wherein the second device driver is a hardware device module.
Claim 13
Dependent Claim
108 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; and second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge.
Claim 14
Dependent Claim
108 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; and second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge.
Claim 15
Dependent Claim
18 words
The data processing system of claim 11 further comprising a second input/output platform connected to the primary bus.
Claim 16
Dependent Claim
124 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; and means for shifting workload from the primary bus to the secondary bus, wherein bandwidth is increased.
Claim 17
Dependent Claim
124 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; and means for shifting workload from the primary bus to the secondary bus, wherein bandwidth is increased.
Claim 18
Dependent Claim
148 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; a plurality of functions are performed by the input/output platform; and assignment means for assigning a portion of the plurality of functions to the processor in the bus bridge, wherein workload is divided between the bus bridge and the input/output platform.
Claim 19
Dependent Claim
148 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; a plurality of functions are performed by the input/output platform; and assignment means for assigning a portion of the plurality of functions to the processor in the bus bridge, wherein workload is divided between the bus bridge and the input/output platform.
Claim 20
Dependent Claim
35 words
The data processing system of claim 14, wherein the portion of the plurality of functions are embodied in a device driver and wherein the assignment means loads the device driver on to the bus bridge.
Claim 21
Dependent Claim
16 words
The data processing system of claim 15, wherein the device driver is an intermediate service module.
Claim 22
Dependent Claim
19 words
The data processing system of claim 14, wherein the portion of the plurality of functions is a RAID function.
Claim 23
Dependent Claim
133 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; a second secondary bus; and a second bus bridge, wherein the second bus bridge provides communications between the first secondary bus and the second secondary bus.
Claim 24
Dependent Claim
133 words
A data processing system comprising: a primary bus; a host processor connected to the primary bus; a secondary bus; a bus bridge connecting the primary bus to the secondary bus, wherein the bus bridge includes: a processor; an input/output platform connected to the secondary bus; first message means for sending messages to the input/output platform from the bus bridge, wherein a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; second message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge; a second secondary bus; and a second bus bridge, wherein the second bus bridge provides communications between the first secondary bus and the second secondary bus.
Claim 25
Dependent Claim
84 words
The data processing system of claim 18 further comprising: a second input/output platform connected to the second secondary bus, third message means for sending messages to the input/output platform from the bus bridge and in which a message generated by the processor in the bus bridge includes an identifier that identifies the message as originating from the host processor; and fourth message means for identifying messages to the host processor that originated from the bus bridge and routing the messages to the bus bridge.
Claim 26
Dependent Claim
88 words
A bus bridge for providing communications between a primary bus and a secondary bus, the apparatus bus bridge comprising: a processor including first instruction means for sending a message to an input/output platform connected to the secondary bus, wherein the message identifies a host processor as an originator of the message; second instruction means for identifying message targeting the host processor as a reply to a message originated by the processor; and third instruction means, for routing the message, identified by the second instruction means, to the processor.
Claim 27
Dependent Claim
88 words
A bus bridge for providing communications between a primary bus and a secondary bus, the apparatus bus bridge comprising: a processor including first instruction means for sending a message to an input/output platform connected to the secondary bus, wherein the message identifies a host processor as an originator of the message; second instruction means for identifying message targeting the host processor as a reply to a message originated by the processor; and third instruction means, for routing the message, identified by the second instruction means, to the processor.
Claim 28
Dependent Claim
112 words
A bus bridge for providing communications between a primary bus and a secondary bus, the apparatus bus bridge comprising: a processor including first instruction means for sending a message to an input/output platform connected to the secondary bus, wherein the message identifies a host processor as an originator of the message; second instruction means for identifying message targeting the host processor as a reply to a message originated by the processor; third instruction means, for routing the message, identified by the second instruction means, to the processor; and fourth instruction means for performing a function for the input/output platform, wherein instruction means for performing the function on the input/output platform are absent.
Claim 29
Dependent Claim
112 words
A bus bridge for providing communications between a primary bus and a secondary bus, the apparatus bus bridge comprising: a processor including first instruction means for sending a message to an input/output platform connected to the secondary bus, wherein the message identifies a host processor as an originator of the message; second instruction means for identifying message targeting the host processor as a reply to a message originated by the processor; third instruction means, for routing the message, identified by the second instruction means, to the processor; and fourth instruction means for performing a function for the input/output platform, wherein instruction means for performing the function on the input/output platform are absent.
Claim 30
Dependent Claim
15 words
The bus bridge of claim 21, wherein the fourth instruction means is a device driver.
Claim 31
Dependent Claim
15 words
The bus bridge of claim 22, wherein the device driver is an intermediate service module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-16 | 2003-11-15 | 2004-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-16 | 2007-11-15 | 2008-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-16 | 2011-11-15 | 2012-05-16 | $7700.00 | Window Closed / Lapsed |