Gate structure of a semiconductor device having an air gap

Claim 2

A gate structure, comprising: a semiconductor substrate; an oxide layer located over the substrate; a conductive layer formed on the oxide layer, wherein an upper portion of the conductive layer is wider than a lower portion of the conductive layer, and the width of the lower portion of the conductive layer is substantially equal to the width of the oxide layer to closely align therewith; a spacer surrounding a side wall of the conductive layer and the oxide layer, wherein the spacer is not directly connected with the conductive layer and the height of the spacer is lower than the upper portion of the conductive layer; and an air gap located between the conductive layer and the spacer to expose a portion of the substrate, wherein the conductive layer overhangs the air gap.

Claim 3

The gate structure according to claim 1, wherein the oxide layer includes a silicon oxide layer having a thickness of about 100 Å to 250 Å.

Claim 4

The gate structure according to claim 1, wherein the conductive layer includes a poly-silicon layer.

Claim 5

The gate structure according to claim 3, wherein the poly-silicon layer has a thickness of about 2000 Å to 3000 Å.

Claim 6

The gate structure according to claim 1, wherein a source/drain region is further comprised in the substrate.

Claim 7

The gate structure according to claim 1, wherein the source/drain region is formed by a process of lightly doped drain.

Claim 8

A semiconductor device having a gate-side air-gap structure, comprising: a semiconductor substrate; a source/drain region formed in the substrate, wherein the source/drain region comprises a source region and a drain region; a gate oxide layer on the substrate between the source region and the drain region; a conductive layer formed on the gate oxide layer, wherein an upper portion of the conductive layer is wider than a lower portion of the conductive layer, and the width of the lower portion of the conductive layer is substantially equal to the width of the oxide layer to closely align therewith; a spacer surrounding a side wall of the conductive layer and the gate oxide layer, wherein the spacer is not directly connected with the conductive layer and the height of the spacer is lower than the upper portion of the conductive layer; and an air gap located between the conductive layer and the spacer to expose a portion of the substrate, wherein the conductive layer overhangs the air gap.

Claim 9

A semiconductor device having a gate-side air-gap structure, comprising: a semiconductor substrate; a source/drain region formed in the substrate, wherein the source/drain region comprises a source region and a drain region; a gate oxide layer on the substrate between the source region and the drain region; a conductive layer formed on the gate oxide layer, wherein an upper portion of the conductive layer is wider than a lower portion of the conductive layer, and the width of the lower portion of the conductive layer is substantially equal to the width of the oxide layer to closely align therewith; a spacer surrounding a side wall of the conductive layer and the gate oxide layer, wherein the spacer is not directly connected with the conductive layer and the height of the spacer is lower than the upper portion of the conductive layer; and an air gap located between the conductive layer and the spacer to expose a portion of the substrate, wherein the conductive layer overhangs the air gap.

Claim 10

The semiconductor device according to claim 7, wherein the gate oxide layer includes a silicon oxide layer having a thickness of about 100 Å to 250 Å.

Claim 11

The semiconductor device according to claim 7, wherein the conductive layer includes a poly-silicon layer.

Claim 12

The semiconductor device according to claim 9, wherein the poly-silicon layer has a thickness of about 2000 Å to 3000 Å.