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US6061709A
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Integrated hardware and software task control executive
Assignee: Wind River Systems Inc
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Filing: 1998-07-31
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Granted: 2000-05-09
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Expires: 2018-07-31
Abstract
Abstract A method and system for permitting a software-based executive to execute concurrently with a hardware-based executive. The software-based executive allocates hardware executive tasks, hardware executive interrupts, software executive tasks, and software executive interrupts to defined execution spaces available on a microprocessor having a hardware-based executive. Applications control hardware-based executive tasks and interrupts through a hardware executive application programming interface (API), and software-based executive tasks through a software executive API. Applications share the hardware executive API functions for interrupt installation and management. The invention allocates all hardware executive interrupts to a high priority interrupt execution space, and all hardware executive tasks to a high priority queue. All software executive interrupts are allocated to low priority interrupts, and all software executive tasks are allocated to a low priority queue. The software executive uses a special context switch mechanism that changes the currently executing task without creating another low priority task. In this way, the low priority hardware scheduler is always disabled, and low priority tasks are always under the control of the software executive. A hierarchical "enables" mechanism protects critical sections of code during reentrancies. An interrupt return revectoring mechanism is provided to provide a mechanism for preemption. When a software executive interrupt occurs, the interrupt return revectoring mechanism exits the interrupt and revectors into the software kernel so that a new kernel task can begin executing, rather than returning to the previously executing task. A mechanism is also provided to accommodate block move operations.
Inventors
- 👤 Jeffrey S. Bronte
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:42
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
170 words
A method for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the method including the steps of: (a) allocating all tasks controlled by the software executive to the low priority task execution queue; (b) allocating all software interrupts to the low priority interrupt execution space; (c) allocating all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and (d) allocating all hardware interrupts to the high priority interrupt execution space; whereby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.
Claim 2
Independent Claim
170 words
A method for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the method including the steps of: (a) allocating all tasks controlled by the software executive to the low priority task execution queue; (b) allocating all software interrupts to the low priority interrupt execution space; (c) allocating all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and (d) allocating all hardware interrupts to the high priority interrupt execution space; whereby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.
Claim 3
Dependent Claim
26 words
The method of claim 1, further including the step of disabling all interrupts within the microprocessor except for trap enables during a context switch between tasks.
Claim 4
Dependent Claim
37 words
The method of claim 1, further including the step of selectively disabling only those interrupts within the microprocessor allocated to the software executive when necessary to enable the hardware executive and hardware interrupts to operate substantially uninhibited.
Claim 5
Dependent Claim
28 words
The method of claim 3, wherein the step of selectively disabling includes the step of asserting a low priority external event disable signal controlled by the hardware executive.
Claim 6
Dependent Claim
64 words
The method of claim 1, further including the step of disabling those interrupts within the microprocessor allocated to the software executive and interrupts selected by a mask and allocated to the hardware executive when necessary to preserve the mask as the mask existed when a kernel call has been invoked, thereby allowing the mask to be restored when the kernel call has been completed.
Claim 7
Dependent Claim
35 words
The method of claim 1, further including the step of permitting a hierarchical selectivity of preemption of tasks, including revectoring returns from pre-empted tasks to the software executive to enable execution of a new task.
Claim 8
Dependent Claim
97 words
The method of claim 1, further including the steps of: (a) setting a flag in an interrupt controller of the microprocessor; (b) generating a hardware interrupt signal in response to the setting of such flag; (c) invoking a low priority interrupt routine allocated to the software executive in response to such interrupt; (d) executing a kernel call in the software executive from within such low priority interrupt routine; whereby a task or interrupt within the hardware executive can indirectly cause execution of the kernel call in the software executive by inducing an interrupt upon setting such flag.
Claim 9
Dependent Claim
123 words
The method of claim 1, further including the steps of: (a) detecting when a block move operation is in progress when an interrupt occurs by monitoring a block move status flag within the microprocessor; (b) storing a value indicating that a block move operation is being interrupted; (c) re-setting the block move status flag within the microprocessor to a value that indicates no block move operation is being executed; (d) processing the interrupt; (e) setting the block move status flag within the microprocessor to the stored value to indicate that a block move operation was being executed, thereby allowing the microprocessor to complete the block move operation; whereby executing block move operations within the microprocessor are preserved for the duration of an interrupt.
Claim 10
Dependent Claim
180 words
A computer program, residing on a computer-readable medium, for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the computer program comprising instructions for causing the microprocessor to: (a) allocate all tasks controlled by the software executive to the low priority task execution queue; (b) allocate all software interrupts to the low priority interrupt execution space; (c) allocate all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and (d) allocate all hardware interrupts to the high priority interrupt execution space; whereby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.
Claim 11
Dependent Claim
180 words
A computer program, residing on a computer-readable medium, for integrating a software executive within a microprocessor having an integral hardware executive, the microprocessor including a high priority scheduler, a high priority interrupt execution space, a low priority interrupt execution space, a high priority task execution queue, and a low priority task execution queue, the computer program comprising instructions for causing the microprocessor to: (a) allocate all tasks controlled by the software executive to the low priority task execution queue; (b) allocate all software interrupts to the low priority interrupt execution space; (c) allocate all tasks controlled by the high priority scheduler of the hardware executive to the high priority task execution queue; and (d) allocate all hardware interrupts to the high priority interrupt execution space; whereby all low priority tasks are under the control of the software executive and all high priority tasks are under the control of the hardware executive, thereby permitting hardware processes within the microprocessor to be serviced by the hardware executive as high priority tasks without interruption by tasks under the control of the software executive.
Claim 12
Dependent Claim
30 words
The computer program of claim 9, further including instructions for causing the microprocessor to disable all interrupts within the microprocessor except for trap enables during a context switch between tasks.
Claim 13
Dependent Claim
41 words
The computer program of claim 9, further including instructions for causing the microprocessor to selectively disable only those interrupts within the microprocessor allocated to the software executive when necessary to enable the hardware executive and hardware interrupts to operate substantially uninhibited.
Claim 14
Dependent Claim
32 words
The computer program of claim 11, wherein instructions for causing the microprocessor to selectively disable includes the step of asserting a low priority external event disable signal controlled by the hardware executive.
Claim 15
Dependent Claim
68 words
The computer program of claim 9, further including instructions for causing the microprocessor to disable those interrupts within the microprocessor allocated to the software executive and interrupts selected by a mask and allocated to the hardware executive when necessary to preserve the mask as the mask existed when a kernel call has been invoked, thereby allowing the mask to be restored when the kernel call has been completed.
Claim 16
Dependent Claim
39 words
The computer program of claim 9, further including instructions for causing the microprocessor to permit a hierarchical selectivity of preemption of tasks, including revectoring returns from preempted tasks to the software executive to enable execution of a new task.
Claim 17
Dependent Claim
101 words
The computer program of claim 9, further including instructions for causing the microprocessor to: (a) set a flag in an interrupt controller of the microprocessor; (b) generate a hardware interrupt signal in response to the setting of such flag; (c) invoke a low priority interrupt routine allocated to the software executive in response to such interrupt; (d) execute a kernel call in the software executive from within such low priority interrupt routine; whereby a task or interrupt within the hardware executive can indirectly cause execution of the kernel call in the software executive by inducing an interrupt upon setting such flag.
Claim 18
Dependent Claim
127 words
The computer program of claim 9, further including instructions for causing the microprocessor to: (a) detect when a block move operation is in progress when an interrupt occurs by monitor a block move status flag within the microprocessor; (b) store a value indicating that a block move operation is being interrupted; (c) re-set the block move status flag within the microprocessor to a value that indicates no block move operation is being executed; (d) process the interrupt; (e) set the block move status flag within the microprocessor to the stored value to indicate that a block move operation was being executed, thereby allowing the microprocessor to complete the block move operation; whereby executing block move operations within the microprocessor are preserved for the duration of an interrupt.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |