Control method for message communication in network supporting software emulated modules and hardware implemented modules

Claim 1

A network utilizing digital hardware modules and software emulated digital modules placed as software in Main System Memory, wherein a Central Processing Module, a PC Processor, and Main System Memory providing, for each one of N modules, a dedicated message queue, identified by a queue number, having "M" message slots, which modules are connected via a system bus which bridges to a PCI bus holding a plurality of hardware Input/Output Modules and a hardware Auxiliary Message Control Module providing algorithmic control sequences for sending messages to dedicated queues in Main System Memory for retrieval by a receiving destination module and utilizing a Token RAM to provide sequential token values for sending modules to access Main Memory plus utilizing a Control RAM with Read, Write and Interrupt pointers for said algorithmic control sequences, a method for regulating the transfer of messages between sending modules and receiving modules, including the steps of: (a) establishing a separate queue in a Main System Memory for each one of said "N" digital modules in the network; (b) assigning each digital module a message-queue number which represents a series of "M" message holding slots in each one of said N message queues dedicated to each particular receiving destination module, each said message queue having Flag means to indicate that the queue is "Empty" or "Not Empty"; (c) providing a Token value to a requesting sending module which Token value identifies a particular message slot in a message queue dedicated to said receiving destination module said Token value being provided in such a rapid sequential fashion so as to prevent any lockup with a concurrently requesting sending module; (d) receiving, by said sending module, of said provided Token value and using it to calculate a Main System Memory address for placing a message destined for said receiving destination module; (e) writing a message from said message-sending module into the main Memory queue in the slot designated by said Token value; (f) returning the Token value, by said sending module, back to said Token RAM, thus indicating that the message from the sending module is now residing in the addressed Main Memory queue and slot for the receiving destination module; (g) signaling an Interrupt to the receiving destination module to indicate that a message is waiting for it; (h) receiving of the Interrupt by the receiving destination module in order to execute a "Get Message" operation via said Auxiliary Message Control Module to said Main System Memory; (i) providing a Token value from said Auxiliary Message Control Module, to said receiving module, which can be used to calculate the System Main Memory address where the message is stored said token value being provided to said receiving module in such a rapid sequential fashion so as to prevent any lockup with a concurrently requesting receiving module; (j) reading, by said receiving destination module, the message residing in said message queue in said Main System Memory; (k) returning, by said receiving destination module, of the message Token value just used, back to said Token RAN in said Auxiliary Message Control Module.

Claim 8

A system for regulating the sequential transfer of messages between multiple sending modules and multiple receiving modules in a network utilizing a message control system whereby no possible deadlock can occur between two concurrently requesting modules seeking a message token, and wherein the network utilizes digital hardware modules and software emulated digital modules which are placed as software in main system memory, and wherein a central processing module, an auxiliary processor utilizes a main system memory to provide a dedicated message queue for each of "N" digital modules, each identified by a queue number having "M" message slots, which modules are connected via a system bus which bridges to a PCI bus holding a plurality of hardware input/output modules and a hardware Auxiliary Message Control module providing algorithmic control sequences for sending messages to dedicated queues in main system memory for retrieval by a receiving destination module and utilizing a Token RAM to provide sequential Token values in order to access main memory, and additionally utilizing a Control RAM with Read, Write, and Interrupt pointers for said algorithmic control sequences, said system ensuring that all messages will be transferred in the proper time sequential order and with no delays due to deadlocks, said system comprising: (a) queue means in said main system memory being dedicated for each one of said "N" digital modules in the network; (b) means to provide each digital module in said network with a message-queue number, which represents a series of "M" message holding slots in each one of said "N" message queues dedicated to each particular destination module; (c) token RAM means to provide a token value to each requesting module whereby said token value identifies a particular message slot in a message queue dedicated to the said receiving destination module said token value being provided in a rapid sequential fashion which will prevent any deadlock condition with other requesting modules; (d) means, in a said sending module, to calculate a main system memory address for placing a message in it destined for said receiving destination module; (e) means to place a message from said message-sending module into the main memory queue in the slot designated by said token value; (f) means, in said sending module, to return the token value back to said token RAM to indicate that the message from the sending module is now residing in the addressed main memory queue and numbered slot for the receiving destination module; (g) means to signal with an interrupt signal to the receiving destination module to indicate that a message is waiting for the said receiving destination modules; (h) means by said destination module to execute a "get message" operation via said Auxiliary Message Control module to said main system memory; (i) means in said Auxiliary Message Control module to provide a token value to said receiving module which can be used by said receiving module to calculate the system main memory address where the message is stored; (j) means in said receiving destination module to access and read the message residing in said message queue in said main system memory; (k) means in said receiving destination module to return the message token value just used, back to said token RAM in said Auxiliary Message Control module.

Claim 9

A system for regulating the sequential transfer of messages between multiple sending modules and multiple receiving modules in a network utilizing a message control system whereby no possible deadlock can occur between two concurrently requesting modules seeking a message token, and wherein the network utilizes digital hardware modules and software emulated digital modules which are placed as software in main system memory, and wherein a central processing module, an auxiliary processor utilizes a main system memory to provide a dedicated message queue for each of "N" digital modules, each identified by a queue number having "M" message slots, which modules are connected via a system bus which bridges to a PCI bus holding a plurality of hardware input/output modules and a hardware Auxiliary Message Control module providing algorithmic control sequences for sending messages to dedicated queues in main system memory for retrieval by a receiving destination module and utilizing a Token RAM to provide sequential Token values in order to access main memory, and additionally utilizing a Control RAM with Read, Write, and Interrupt pointers for said algorithmic control sequences, said system ensuring that all messages will be transferred in the proper time sequential order and with no delays due to deadlocks, said system comprising: (a) queue means in said main system memory being dedicated for each one of said "N" digital modules in the network; (b) means to provide each digital module in said network with a message-queue number, which represents a series of "M" message holding slots in each one of said "N" message queues dedicated to each particular destination module; (c) token RAM means to provide a token value to each requesting module whereby said token value identifies a particular message slot in a message queue dedicated to the said receiving destination module said token value being provided in a rapid sequential fashion which will prevent any deadlock condition with other requesting modules; (d) means, in a said sending module, to calculate a main system memory address for placing a message in it destined for said receiving destination module; (e) means to place a message from said message-sending module into the main memory queue in the slot designated by said token value; (f) means, in said sending module, to return the token value back to said token RAM to indicate that the message from the sending module is now residing in the addressed main memory queue and numbered slot for the receiving destination module; (g) means to signal with an interrupt signal to the receiving destination module to indicate that a message is waiting for the said receiving destination modules; (h) means by said destination module to execute a "get message" operation via said Auxiliary Message Control module to said main system memory; (i) means in said Auxiliary Message Control module to provide a token value to said receiving module which can be used by said receiving module to calculate the system main memory address where the message is stored; (j) means in said receiving destination module to access and read the message residing in said message queue in said main system memory; (k) means in said receiving destination module to return the message token value just used, back to said token RAM in said Auxiliary Message Control module.