Patent US6061292A successfully refreshed from Google Patents.
US6061292A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit for triggering column select line for write operations
Assignee: Winbond Electronics Corp
•
Filing: 1998-11-18
•
Granted: 2000-05-09
•
Expires: 2018-11-18
Abstract
Abstract Methods and circuits for triggering column select line for write operations in a multiple data rate (e.g., a double data rate) operation. A memory device includes a memory array that stores data values, an address logic circuit that generates an address for the memory array, and a column decoder. The column decoder couples to the address logic circuit and the memory array. The column decoder receives either a data strobe input signal (DQS) or a clock signal (CLK), or both, and activates a column select line for the memory array in response to one of the input signal(s).
Inventors
- 👤 Teng Su
- 👤 Hua Zheng
- 👤 Kamin Fei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1066; G11C7/22; G11C8/00; G11C8/10
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
100 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line corresponding to the generated address for the memory array, wherein the column select line is activated based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory array.
Claim 2
Independent Claim
100 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line corresponding to the generated address for the memory array, wherein the column select line is activated based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory array.
Claim 3
Dependent Claim
18 words
The device of claim 1, wherein the data strobe signal and the clock signal conform to JEDEC standards.
Claim 4
Dependent Claim
20 words
The device of claim 1, wherein the column select line is activated based on rising edges of the clock signal.
Claim 5
Dependent Claim
20 words
The device of claim 1, wherein the column select line is activated based on falling edges of the clock signal.
Claim 6
Dependent Claim
17 words
The device of claim 1, wherein the column select line is delayed by a particular time period.
Claim 7
Dependent Claim
13 words
The device of claim 1, wherein the memory device operates in multi-data rate.
Claim 8
Dependent Claim
15 words
The device of claim 1, wherein the memory device operates in double data rate (DDR).
Claim 9
Dependent Claim
12 words
A dynamic random access memory (DRAM) comprising the device of claim 1.
Claim 10
Dependent Claim
13 words
A synchronous graphics random access memory (SGRAM) comprising the device of claim 1.
Claim 11
Dependent Claim
14 words
An integrated circuit comprising an embedded memory array and the device of claim 1.
Claim 12
Independent Claim
82 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is triggered using the data strobe signal during write operations.
Claim 13
Independent Claim
82 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is triggered using the data strobe signal during write operations.
Claim 14
Independent Claim
81 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is triggered using the clock signal during read operations.
Claim 15
Independent Claim
81 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is triggered using the clock signal during read operations.
Claim 16
Independent Claim
83 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is activated based on falling edges of the data strobe signal.
Claim 17
Independent Claim
83 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, wherein the column select line is activated based on falling edges of the data strobe signal.
Claim 18
Independent Claim
101 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, a multiplexer coupled to the column decoder, the multiplexer configured to receive the data strobe signal and the clock signal and to provide an output signal based on an operating mode of the device.
Claim 19
Independent Claim
101 words
A device comprising: a memory array configured to store data values; an address logic circuit configured to generate an address for the memory array; and a column decoder coupled to the address logic circuit and the memory array, the column decoder configured to receive at least one of a data strobe signal and a clock signal and to activate a column select line for the memory array, a multiplexer coupled to the column decoder, the multiplexer configured to receive the data strobe signal and the clock signal and to provide an output signal based on an operating mode of the device.
Claim 20
Dependent Claim
29 words
The device of claim 14, wherein the multiplexer provides the data strobe signal to the column decoder during a write operation and the clock signal during a read operation.
Claim 21
Dependent Claim
12 words
A dynamic random access memory (DRAM) comprising the device of claim 14.
Claim 22
Dependent Claim
13 words
The device of claim 14, wherein the memory device operates in multi-data rate.
Claim 23
Independent Claim
84 words
A method for performing a write of data bits to memory cells within a memory array comprising: receiving at least one of a data strobe signal and a clock signal; receiving the data bits; activating a column select line for the memory array based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory device; and writing the data bits to memory cells within the memory device identified, in part, by the column select line.
Claim 24
Independent Claim
84 words
A method for performing a write of data bits to memory cells within a memory array comprising: receiving at least one of a data strobe signal and a clock signal; receiving the data bits; activating a column select line for the memory array based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory device; and writing the data bits to memory cells within the memory device identified, in part, by the column select line.
Claim 25
Dependent Claim
18 words
The method of claim 18, wherein the data strobe signal and the clock signal conform to JEDEC standard.
Claim 26
Dependent Claim
21 words
The method of claim 18, wherein the column select line is triggered based on falling edges of the data strobe signal.
Claim 27
Dependent Claim
20 words
The method of claim 18, wherein the column select line is triggered based on rising edges of the clock signal.
Claim 28
Dependent Claim
20 words
The method of claim 18, wherein the column select line is triggered based on falling edges of the clock signal.
Claim 29
Dependent Claim
17 words
The method of claim 18, wherein the column select line is delayed by a particular delay period.
Claim 30
Dependent Claim
15 words
The method of claim 18, wherein the memory array is operated in a multi-data rate.
Claim 31
Dependent Claim
17 words
The method of claim 18, wherein the memory array is operated in a double data rate (DDR).
Claim 32
Dependent Claim
21 words
The method of claim 18, wherein the column select line is activated based on a particular timing of the data bits.
Claim 33
Independent Claim
87 words
A method for accessing a memory array comprising: receiving at least one of a data strobe signal and a clock signal; generating an address for the memory array; activating a column select line corresponding to the generated address, wherein the column select line is activated based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory device; and performing a memory access of memory cells within the memory array identified, in part, by the activated column select line.
Claim 34
Independent Claim
87 words
A method for accessing a memory array comprising: receiving at least one of a data strobe signal and a clock signal; generating an address for the memory array; activating a column select line corresponding to the generated address, wherein the column select line is activated based on either the data strobe signal or the clock signal depending on a particular operating mode of the memory device; and performing a memory access of memory cells within the memory array identified, in part, by the activated column select line.
Claim 35
Dependent Claim
13 words
The method of claim 27, wherein the memory access is a read operation.
Claim 36
Dependent Claim
13 words
The method of claim 27, wherein the memory access is a write operation.
Claim 37
Dependent Claim
31 words
The method of claim 27, wherein the column select line is activated based on a particular timing of data bits to be written to the memory array during a write operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |