US6060749A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Ultra-short channel elevated S/D MOSFETS formed on an ultra-thin SOI substrate
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1998-04-23
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Granted: 2000-05-09
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Expires: 2018-04-23
Abstract
Abstract The present invention includes a SOI structure formed in a substrate. A gate is formed over the substrate in a recessed portion of a substrate. A first isolation structure is formed on the side walls of the gate. A second isolation structure is formed adjacent to the first isolation structure. Source and drain regions are formed on the SOI structure. Lightly doped drain (LDD) structures are formed adjacent to the source and drain regions, on the SOI structure and under the second isolation structure. A first metal silicide layer is formed on the source and drain regions and a second metal silicide layer is formed on the gate.
Inventors
- 👤 Shye-Lin Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:27
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6757; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0323; H10D30/0212; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
187 words
A structure for forming a transistor with ultra short channel and elevated source and drain on a substrate, said structure comprising: a silicon on insulator (SOI) structure formed in said substrate and said SOI structure keeping a space from a surface of said substrate, thereby creating a silicon layer formed thereon, wherein said substrate has a recessed portion formed in said silicon layer; an oxide layer formed on said surface of said substrate; a field oxide region formed on said recessed portion, said field oxide region having a first opening formed therein thereby exposing a portion of said silicon layer, wherein said opening is used for filling a gate therein, said silicon layer under said field oxide region having a thinner portion and thicker portions, wherein said thicker portion is used to form said elevated source and drain; a mask structure having a second opening wider than said first opening formed on said oxide layer; and spacers formed on said field oxide and attached on side walls of said second opening, wherein said spacers and said mask structure are used in combination to form said first opening.
Claim 2
Dependent Claim
187 words
A structure for forming a transistor with ultra short channel and elevated source and drain on a substrate, said structure comprising: a silicon on insulator (SOI) structure formed in said substrate and said SOI structure keeping a space from a surface of said substrate, thereby creating a silicon layer formed thereon, wherein said substrate has a recessed portion formed in said silicon layer; an oxide layer formed on said surface of said substrate; a field oxide region formed on said recessed portion, said field oxide region having a first opening formed therein thereby exposing a portion of said silicon layer, wherein said opening is used for filling a gate therein, said silicon layer under said field oxide region having a thinner portion and thicker portions, wherein said thicker portion is used to form said elevated source and drain; a mask structure having a second opening wider than said first opening formed on said oxide layer; and spacers formed on said field oxide and attached on side walls of said second opening, wherein said spacers and said mask structure are used in combination to form said first opening.
Claim 3
Dependent Claim
13 words
The structure of claim 1, wherein said mask structure is formed of nitride.
Claim 4
Dependent Claim
12 words
The structure of claim 1, wherein said spacers is formed of nitride.
Claim 5
Dependent Claim
30 words
The structure of claim 1, further comprising an oxynitride layer formed along a surface of said mask structure, said spacers and said second opening to act as a gate dielectric.
References Cited (Backward Citations)
US5736751A
Cited
US5296727A
Cited
US5475244A
Cited
US5349228A
Cited
US5550397A
Cited
US5684318A
Cited
US5567966A
Cited
US5418391A
Cited
US5729039A
Cited
US5557126A
Cited
US5693959A
Cited
US5925918A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2003-05-09 | 2003-11-08 | 2004-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2007-05-09 | 2007-11-08 | 2008-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2011-05-09 | 2011-11-08 | 2012-05-09 | $7700.00 | Window Closed / Lapsed |