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US6054343A Expired / Lapsed US ⏱️ 0.0 years remaining

Nitride trench fill process for increasing shallow trench isolation (STI) robustness

Assignee: Texas Instruments Inc
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Filing: 1999-01-20
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Granted: 2000-04-25
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Expires: 2019-01-20
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Abstract

Abstract A semiconductor device and method having shallow trench isolation. A pad oxide 24 and silicon 42 are formed on a substrate 20 to form a mask, and the pad oxide 24/silicon 42 mask is then patterned. Portions of the pad oxide 24/silicon 42 mask and the substrate 20 are removed to form trenches 22 in the substrate 20. A nitride fill 40 is deposited over the pad oxide 24/silicon 42 mask and the trenches 22. Advantages of the invention include a more robust STI device without central voids 34 and without edge voids 36 in the trench fill material.

Inventors

  • 👤 Stanton Ashburn

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-31 12:12
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/014; H10W10/10; H10W10/17

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 137 words
A method for manufacturing a semiconductor device having shallow trench isolation, comprising the steps of: providing a substrate; forming a pad oxide/silicon mask on said substrate; patterning said pad oxide/silicon mask; removing portions of said pad oxide/silicon mask and said substrate to form a trench in said substrate, said trench having a bottom and sidewalls; forming a liner oxide on said bottom and said sidewalls of said trench and concurrently oxidizing exposed portions of said silicon mask extending over the corners of said trench; depositing a nitride fill over said pad oxide/silicon mask and said trench; and removing the unoxidized portion of said silicon mask and the oxidized portion of said silicon mask not extending over the corners of said trench while retaining the oxidized portions of said silicon mask extending over said corners of said trench.
Claim 2
Independent Claim 137 words
A method for manufacturing a semiconductor device having shallow trench isolation, comprising the steps of: providing a substrate; forming a pad oxide/silicon mask on said substrate; patterning said pad oxide/silicon mask; removing portions of said pad oxide/silicon mask and said substrate to form a trench in said substrate, said trench having a bottom and sidewalls; forming a liner oxide on said bottom and said sidewalls of said trench and concurrently oxidizing exposed portions of said silicon mask extending over the corners of said trench; depositing a nitride fill over said pad oxide/silicon mask and said trench; and removing the unoxidized portion of said silicon mask and the oxidized portion of said silicon mask not extending over the corners of said trench while retaining the oxidized portions of said silicon mask extending over said corners of said trench.
Claim 3
Dependent Claim 29 words
The method of claim 1, further comprising the step of removing portions of said nitride fill residing over said pad oxide/silicon mask, after said step of depositing a nitride.
Claim 4
Dependent Claim 23 words
The method of claim 2, further comprising the step of depositing a gate oxide, after said step of removing said pad oxide/silicon mask.
Claim 5
Dependent Claim 17 words
The method of claim 1, wherein said step of depositing a nitride fill comprises depositing silicon nitride.
Claim 6
Dependent Claim 17 words
The method of claim 1, wherein said step of depositing a nitride fill comprises depositing boron nitride.
Claim 7
Independent Claim 138 words
A method for manufacturing a semiconductor device having shallow trench isolation, comprising the steps of: providing a substrate; forming a pad oxide/silicon mask on said substrate; patterning said pad oxide/silicon mask; removing portions of said pad oxide/silicon mask and said substrate to form a trench in said substrate, said trench having a bottom and sidewalls; forming a liner oxide on said bottom and said sidewalls of said trench and concurrently oxidizing exposed portions of said silicon mask extending over the corners of said trench; depositing a nitride fill over said pad oxide/silicon mask and said liner oxide; and removing the unoxidized portion of said silicon mask and the oxidized portion of said silicon mask not extending over the corners of said trench while retaining the oxidized portions of said silicon mask extending over said corners of said trench.
Claim 8
Independent Claim 138 words
A method for manufacturing a semiconductor device having shallow trench isolation, comprising the steps of: providing a substrate; forming a pad oxide/silicon mask on said substrate; patterning said pad oxide/silicon mask; removing portions of said pad oxide/silicon mask and said substrate to form a trench in said substrate, said trench having a bottom and sidewalls; forming a liner oxide on said bottom and said sidewalls of said trench and concurrently oxidizing exposed portions of said silicon mask extending over the corners of said trench; depositing a nitride fill over said pad oxide/silicon mask and said liner oxide; and removing the unoxidized portion of said silicon mask and the oxidized portion of said silicon mask not extending over the corners of said trench while retaining the oxidized portions of said silicon mask extending over said corners of said trench.
Claim 9
Dependent Claim 30 words
The method of claim 6, further comprising the step of removing portions of said nitride fill residing over said pad oxide/silicon mask, after said step of depositing a nitride fill.
Claim 10
Dependent Claim 23 words
The method of claim 7, further comprising the step of depositing a gate oxide, after said step of removing said pad oxide/silicon mask.
Claim 11
Dependent Claim 17 words
The method of claim 6, wherein said step of depositing a nitride fill comprises depositing silicon nitride.
Claim 12
Dependent Claim 17 words
The method of claim 6, wherein said step of depositing a nitride fill comprises depositing boron nitride.

References Cited (Backward Citations)

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US5868870A Cited
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US5436488A Cited
US5766823A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2003-04-25 2003-10-25 2004-04-25 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2007-04-25 2007-10-25 2008-04-25 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2011-04-25 2011-10-25 2012-04-25 $7700.00 Window Closed / Lapsed

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