Clock skew circuit

Claim 2

A clock circuit, comprising: an input terminal for receiving a clock signal; a first pulse generator coupled to said input terminal, said first pulse generator operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of said clock signal; a second pulse generator coupled to said input terminal, said second pulse generator operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of said clock signal; a first clock deskewing circuit coupled between said first pulse generator and a first clock signal output terminal; and a second clock deskewing circuit coupled between said second pulse generator and a second clock signal output terminal.

Claim 3

The clock circuit of claim 1, further comprising: an OR logic circuit coupled to said first and second clock signal output terminals; and a third pulse generator coupled to said OR logic circuit, said third pulse generator having a third clock signal output terminal.

Claim 4

The clock circuit of claim 1, wherein said first and second clock deskewing circuits comprise: a first delay circuit having an input terminal and a plurality of output terminals; a second delay circuit having a plurality of input terminals and an output terminal; and a control circuit coupling each of said plurality of output terminals of said first delay circuit to a corresponding one of said plurality of input terminals of said second delay circuit.

Claim 5

The clock circuit of claim 3, wherein said first and second delay circuits comprise serial-coupled logic gates.

Claim 6

The clock circuit of claim 1, wherein said first pulse generator comprises: a clock signal input terminal; a NAND gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; a first inverter coupled between said clock signal input terminal and said second input terminal of said NAND gate; a clock signal output terminal; and a second inverter coupled between said NAND gate output terminal and said clock signal output terminal.

Claim 7

The clock circuit of claim 1, wherein said second pulse generator comprises: a clock signal input terminal; a NOR gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; and an inverter coupled between said clock signal input terminal and said second input terminal of said NOR gate.

Claim 8

An integrated circuit, comprising: an input terminal for receiving a clock signal; a first pulse generator coupled to said input terminal, said first pulse generator operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of said clock signal; a second pulse generator coupled to said input terminal, said second pulse generator operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of said clock signal; first clock deskewing circuit coupled between said first pulse generator and a first clock signal output terminal; and a second clock deskewing circuit coupled between said second pulse generator and a second clock signal output terminal.

Claim 9

An integrated circuit, comprising: an input terminal for receiving a clock signal; a first pulse generator coupled to said input terminal, said first pulse generator operable to generate a voltage pulse in response to a logic-low voltage to logic-high voltage transition of said clock signal; a second pulse generator coupled to said input terminal, said second pulse generator operable to generate a voltage pulse in response to a logic-high voltage to logic-low voltage transition of said clock signal; first clock deskewing circuit coupled between said first pulse generator and a first clock signal output terminal; and a second clock deskewing circuit coupled between said second pulse generator and a second clock signal output terminal.

Claim 10

The integrated circuit of claim 7, further comprising: an OR logic circuit coupled to said first and second clock signal output terminals; and a third pulse generator coupled to said OR logic circuit, said third pulse generator having a third clock signal output terminal.

Claim 11

The integrated circuit of claim 8, further comprising a data transfer circuit coupled to said third clock signal output terminal.

Claim 12

The integrated circuit of claim 7, wherein said first and second clock deskewing circuits comprise: a first delay circuit having an input terminal and a plurality of output terminals; a second delay circuit having a plurality of input terminals and an output terminal; and a control circuit coupling each of said plurality of output terminals of said first delay circuit to a corresponding one of said plurality of input terminals of said second delay circuit.

Claim 13

The integrated circuit of claim 7, wherein said first pulse generator comprises: a clock signal input terminal; a NAND gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; a first inverter coupled between said clock signal input terminal and said second input terminal of said NAND gate; a clock signal output terminal; and a second inverter coupled between said NAND gate output terminal and said clock signal output terminal.

Claim 14

The integrated circuit of claim 7, wherein said first pulse generator comprises: a clock signal input terminal; a NOR gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; and an inverter coupled between said clock signal input terminal and said second input terminal of said NOR gate.

Claim 15

A dynamic random access memory integrated circuit, comprising: an input terminal for receiving an external clock signal; a first pulse generator coupled to said input terminal, said first pulse generator operable to generate a first internal clock signal in response to a logic-low voltage to logic-high voltage transition of said external clock signal; a second pulse generator coupled to said input terminal, said second pulse generator operable to generate a second internal clock signal in response to a logic-high voltage to logic-low voltage transition of said external clock signal; a first clock deskewing circuit coupled between said first pulse generator and a first clock signal output node; a second clock deskewing circuit coupled between said second pulse generator and a second clock signal output node; a logic circuit coupled to said first and second clock signal output nodes, said logic circuit combining said first and second internal clock signals to produce a third internal clock signal; a third pulse generator coupled to said logic circuit to receive said third internal clock signal, said third pulse generator operable to produce a fourth internal clock signal at an internal clock signal output terminal in response to transitions in said third internal clock signal from a first logic voltage to a second logic voltage; and an output circuit for controlling the transfer of data out of said memory integrated circuit, said output circuit responsive to said fourth internal clock signal in said transfer of data.

Claim 16

A dynamic random access memory integrated circuit, comprising: an input terminal for receiving an external clock signal; a first pulse generator coupled to said input terminal, said first pulse generator operable to generate a first internal clock signal in response to a logic-low voltage to logic-high voltage transition of said external clock signal; a second pulse generator coupled to said input terminal, said second pulse generator operable to generate a second internal clock signal in response to a logic-high voltage to logic-low voltage transition of said external clock signal; a first clock deskewing circuit coupled between said first pulse generator and a first clock signal output node; a second clock deskewing circuit coupled between said second pulse generator and a second clock signal output node; a logic circuit coupled to said first and second clock signal output nodes, said logic circuit combining said first and second internal clock signals to produce a third internal clock signal; a third pulse generator coupled to said logic circuit to receive said third internal clock signal, said third pulse generator operable to produce a fourth internal clock signal at an internal clock signal output terminal in response to transitions in said third internal clock signal from a first logic voltage to a second logic voltage; and an output circuit for controlling the transfer of data out of said memory integrated circuit, said output circuit responsive to said fourth internal clock signal in said transfer of data.

Claim 17

The integrated circuit of claim 13, wherein said logic gate comprises an OR logic circuit.

Claim 18

The integrated circuit of claim 14, wherein said OR logic circuit comprises a NOR gate and an inverter.

Claim 19

The integrated circuit of claim 13, wherein said first and second clock deskewing circuits comprise: a first delay circuit having an input terminal and a plurality of output terminals; a second delay circuit having a plurality of input terminals and an output terminal; and a control circuit coupling each of said plurality of output terminals of said first delay circuit to a corresponding one of said plurality of input terminals of said second delay circuit.

Claim 20

The integrated circuit of claim 13, wherein said first pulse generator comprises: a clock signal input terminal; a NAND gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; a first inverter coupled between said clock signal input terminal and said second input terminal of said NAND gate; a clock signal output terminal; and second inverter coupled between said NAND gate output terminal and said clock signal output terminal.

Claim 21

The integrated circuit of claim 13, wherein said first pulse generator comprises: a clock signal input terminal; a NOR gate having first and second input terminals and an output terminal, said first input terminal coupled to said clock signal input terminal; and an inverter coupled between said clock signal input terminal and said second input terminal of said NOR gate.